Realization of OFDM modulation and demodulation for visible light communication based on FPGA

In order to ensure stable,correct and real-time high-speed transmission of indoor visible light communication(VLC),the key modulation and demodulation technologies of orthogonal frequency division multiplexing(OFDM) are studied in this paper. The time-domain synchronization,frequency synchronization and channel equalization of receiver are analyzed and optimized by utilizing short and long training preamble. Moreover,field programmable gate array(FPGA) development board(Xilinx Kintex-7) and Verilog hardware description language are used to realize the design of proposed OFDM-VLC system. Simulation and experiment both verify the feasibility of the hardware designs of this system. The proposed OFDM-based VLC system can process signal in real-time,which can be used in actual VLC application systems.

A 330-W single-frequency retrievable multi-tone monolithic fiber amplifier

A single-frequency retrievable phase modulated multi-tone fiber amplifier is presented in theory and demonstrated in experiment. A multi-tone seed laser generated by a sine wave phase modulated single-frequency laser is employed for stimulated Brillouin scattering suppression in an all-fiber amplifier. A demodulation signal which is π phase shifted with respect to the modulation signal is used to retrieve the single-frequency laser from the multi-tone laser. In experiment, we first optimize the all-fiber master-oscillator power-amplifier. With this amplifier, we demonstrate a single-frequency retrievable multi-tone laser with 330-W output when driven by the multi-tone seed, while the ultimate output power is only 130 W when driven by the single-frequency laser. Then, we carry out an experiment for retrieving the single-frequency laser from the amplified multi-tone laser. Results indicate that the single-frequency laser can be retrieved with a sideband suppression of more than 20 dB. Retrieving an even higher power single-frequency laser is possible if a high power demodulator is available.

116 dB dynamic range CMOS readout circuit for MEMS capacitive accelerometer

A high stability in-circuit reprogrammable technique control system for a capacitive MEMS accelerometer is presented. Modulation and demodulation are used to separate the signal from the low frequency noise. A low-noise low-offset charge integrator is employed in this circuit to implement a capacitance-to-voltage converter and minimize the noise and offset. The application-specific integrated circuit （ASIC） is fabricated in a 0.5 /μm one-ploy three-metal CMOS process. The measured results of the proposed circuit show that the noise floor of the ASIC is -116 dBV, the sensitivity of the accelerometer is 66 mV/g with a nonlinearity of 0.5%. The chip occupies 3.5×2.5 mm2 and the current is 3.5 mA.