Pushing the high-k scalability limit with a superparaelectric gate layer

To meet the expectation set by Moore’s law on transistors,the search for thickness-scalable high dielectric constant(k)gate layers has become an emergent research frontier.Previous investigations have failed to solve the“polarizability–scalability–insulation robustness”trilemma.In this work,we show that this trilemma can be solved by using a gate layer of a high k ferroelectric oxide in its superparaelectric(SPE)state.In the SPE,its polar order becomes local and is dispersed in an amorphous matrix with a crystalline size down to a few nanometers,leading to an excellent dimensional scalability and a good field-stability of the k value.As an example,a stable high k value(37±3)is shown in ultrathin SPE films of(Ba_(0.95),Sr_(0.05))(Zr_(0.2),Ti_(0.8))O_(3)deposited on LaNiO_(3)-buffered Pt/Ti/SiO_(2)/(100)Si down to a 4 nm thickness,leading to a small equivalent oxide thickness of~0.46 nm.The aforementioned characteristic microstructure endows the SPE film a high breakdown strength(~10.5 MV·cm^(−1)for the 4 nm film),and hence ensures a low leakage current for the operation of the complementary metal oxide semiconductor(CMOS)gate.Lastly,a high electrical fatigue resistance is displayed by the SPE films.These results reveal a great potential of superparaelectric materials as gate dielectrics in the next-generation microelectronics.

Cross-layer efforts for energy-efficient computing:towards peta operations per second per watt

As Moore＇s law based device scaling and accompanying performance scaling trends are slowing down, there is increasing interest in new technologies and computational models for fast and more energy-efficient information processing. Meanwhile, there is growing evidence that, with respect to traditional Boolean circuits and von Neumann processors, it will be challenging for beyond-CMOS devices to compete with the CMOS technology. Exploiting unique characteristics of emerging devices, especially in the context of alternative circuit and architectural paradigms, has the potential to offer orders of magnitude improvement in terms of power, performance, and capability. To take full advantage of beyond-CMOS devices, cross-layer efforts spanning from devices to circuits to architectures to algorithms are indispensable. This study examines energy-efficient neural network accelerators for embedded applications in this context. Several deep neural network accelerator designs based on cross-layer efforts spanning from alternative device technologies, circuit styles, to architectures are highlighted. Application-level benchmarking studies are presented. The discussions demonstrate that cross-layer efforts indeed can lead to orders of magnitude gain towards achieving extreme-scale energy-efficient processing.