Atomic level deposition to extend Moore’s law and beyond

In the past decades,Moore’s law drives the semiconductor industry to continuously shrink the critical size of transistors down to 7 nm.As transistors further downscaling to smaller sizes,the law reaches its limitation,and the increase of transistors density on the chip decelerates.Up to now,extreme ultraviolet lithography has been used in some key steps,and it is facing alignment precision and high costs for high-volume manufacturing.Meanwhile,the introduction of new materials and 3D complex structures brings serious challenges for top-down methods.Thus,bottom-up schemes are believed to be necessary methods combined with the top-down processes.In this article,atomic level deposition methods are reviewed and categorized to extend Moore’s law and beyond.Firstly,the deposition brings lateral angstrom resolution to the vertical direction as well as top-down etching,such as double patterning,transfer of nanowires,deposition of nanotubes,and so on.Secondly,various template-assisted selective deposition methods including dielectric templates,inhibitors and correction steps have been utilized for the alignment of 3D complex structures.Higher resolution can be achieved by inherently selective deposition,and the underlying selective mechanism is discussed.Finally,the requirements for higher precision and efficiency manufacturing are also discussed,including the equipment,integration processes,scale-up issues,etc.The article reviews low dimensional manufacturing and integration of 3D complex structures for the extension of Moore’s law in semiconductor fields,and emerging fields including but not limited to energy,catalysis,sensor and biomedicals.

Study on the Development of the Chip Information Industry Based on Moore’s Law

Chips are the carriers of ICs (integrated circuits). As a result of design, manufacturing, and packaging and testing processes, chips are typically wholly independent entities intended for immediate use. According to known data, one unit of chip output can drive up to ten units of output in the electronic information industry and 100 units of GDP (Gross Domestic Product). The Chip Information Industry is a strategic industry in most developed countries in Europe and North America. The development of the Chip Information Industry is related to national economies and personal livelihoods. Moore discovered a certain trend after analyzing data: in general, every newly produced chip has twice the capacity of the previous generation, and it takes 18 to 24 months for the next generation to be subsequently invented. This trend has come to be known as Moore’s Law. It applies not only to the development of memory chips but also to the evolutionary paths of processor capability and disk drive storage capacity. Moore’s Law has become the basis of performance prediction in several industries. However, since 2011, the size of silicon transistors has been approaching its physical limit at the atomic level. Due to the nature of silicon, additional breakthroughs in the running speed and performance of silicon transistors are severely limited. Elevated temperature and leakage are the two main sources that invalidate Moore’s Law. To counter these issues, This paper analyzes specific problems challenges in the Chip Information Industry, including the development of carbon nanotube chips and fierce competition in the international Chip Information Industry. In addition, this paper undertakes a critical analysis of the Chinese Chip Information Industry and countermeasures to Chinese Chip Information Industry development.

New Approach to Deep Miniaturization: A Way to Overcoming Moore’s Law

The matter about some far-going consequences commencing from the replacement of one of the basic principles of the traditional physics that is the principle of locality, with the recently put forward principle of boundedness is considered. It is proven that the thermodynamic theory which is explicitly grounded on the principle of locality, suffers inherent contradiction which roots lay down to the principle of locality. The way to overcome it goes via the replacement of the principle of locality with the recently put forward by the author principle of boundedness. In turn, the latter gives rise not only to a fundamentally novel notion for a number of ideas but also it yields replacement of the proportionality between the software and hardware components with a new non-extensive approach to the matter. It is proven that the famous Moore’s law stands in new reading both in its support and the way to overcome its limitations. Apart from its role for the technical applications, the present considerations stand also as a methodological example how the role of the basics of any theory affects practical rules such as the Moore’s law.

G-Phenomena as a Base of Scalable Distributed Computing—G-Phenomena in Moore’s Law

Today we witness the exponential growth of scientific research. This fast growth is possible thanks to the rapid development of computing systems since its first days in 1947 and the invention of transistor till the present days with high performance and scalable distributed computing systems. This fast growth of computing systems was first observed by Gordon E. Moore in 1965 and postulated as Moore’s Law. For the development of the scalable distributed computing systems, the year 2000 was a very special year. The first GHz speed processor, GB size memory and GB/s data transmission through network were achieved. Interestingly, in the same year the usable Grid computing systems emerged, which gave a strong impulse to a rapid development of distributed computing systems. This paper recognizes these facts that occurred in the year 2000, as the G-phenomena, a millennium cornerstone for the rapid development of scalable distributed systems evolved around the Grid and Cloud computing paradigms.

The fabrication of ideal diamond disk(IDD)by casting diamond film on silicon wafer

With the relentless densification of interconnected circuitry dictated by Moore’ s Law,the CMP manufacture of such delicate wafers requires the significant reduction of polishing pressure of integrated circuits,not only globally,but also locally on every tip of the pad asperities.Conventional diamond disks used for dressing the polyurethane pads cannot produce asperities to achieve such uniformity.A new design of diamond disk was fabricated by casting diamond film on a silicon wafer that contains patterned etching pits. This silicon mold was subsequently removed by dissolution in a hydroxide solution.The diamond film followed the profile of the etching pits on silicon to form pyramids of identical in size and shape.The variation of their tip heights was in microns of single digit that was about one order of magnitude smaller than conventional diamond disks for CMP production.Moreover,the diamond film contained no metal that might contaminate the circuits on polished wafer during a CMP operation.The continuous diamond film could resist any corrosive attack by slurry of acid or base.Consequently,in-situ dressing during CMP is possible that may improve wafer uniformity and production throughput.This ideal diamond disk(IDD) is designed for the future manufacture of advanced semiconductor chips with node sizes of 32 nm or smaller.

High pressure CMP with low stress polishing

Low stress polishing is required for the manufacture of advanced integrated circuits(IC) with node sizes of 45 nm and smaller.However,the CMP community achieved the low stress by reducing the down force that press the wafer against a rotating pad.The reduced down force also decrease the removal rate of the wafer. As a result,the productivity suffers.In order to cope with this problem,an electrical potential is applied to the copper layer during polishing,in this case,the chemical oxidation is accelearated and hence the removal rate. Alternatively,the rotating pad must be softened to minimize the defects of wafers caused by CMP. In this research,we report a simpler solution to achieve low stress polishing without investing in new equipment and in developing new pad materials.The conventional CMP is proceeded by dressing the pad with a PCD dresser that can form 10×more asperities on the pad surface.The fluffy surface can then polish delicate IC without using the brutal force.As a result,the removal rate of wafers can be maintained without causing defectivity on the IC layer.

The Future of Quantum Computer Advantage

As technological innovations in computers begin to advance past their limit (Moore’s law), a new problem arises: What computational device would emerge after the classical supercomputers reach their physical limitations? At this moment in time, quantum computers are at their starting stage and there are already some strengths and advantages when compared with modern, classical computers. In its testing period, there are a variety of ways to create a quantum computer by processes such as the trapped-ion and the spin-dot methods. Nowadays, there are many drawbacks with quantum computers such as issues with decoherence and scalability, but many of these issues are easily emended. Nevertheless, the benefits of quantum computers at the moment outweigh the potential drawbacks. These benefits include its use of many properties of quantum mechanics such as quantum superposition, entanglement, and parallelism. Using these basic properties of quantum mechanics, quantum computers are capable of achieving faster computational times for certain problems such as finding prime factors of an integer by using Shor’s algorithm. From the advantages such as faster computing times in certain situations and higher computing powers than classical computers, quantum computers have a high probability to be the future of computing after classical computers hit their peak.