Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art

This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.

Effect of Unsteady Secondary Vortices on Performance of a 1.5-Stage High-Pressure Turbine

In modern high-load high-pressure turbine,the secondary flow in the blade channel is very strong and occupies a large spanwise region.Although high-quality experimental data at the stage interfaces have been obtained in previous research,the influence of the clocking position on the secondary flow patterns is not fully understood.This paper investigates the clocking effect in a 1.5-stage high-pressure turbine and focuses on the variations of secondary flow patterns and their effect on the turbine performance.The detailed flow fields of various clocking positions were obtained by carrying out unsteady flow simulations using an in-house code.Among the four clocking positions in this work,the highest entropy generation was observed when the wakes from stator 1 hit the leading edges of stator 2,which is opposite to the well-known conclusion for the turbine with high-aspect-ratio blades.Detailed flow analysis showed that the wakes and the near tip secondary vortices from stator 1 showed different traces when entering the stator 2 channel and the secondary vortices clearly have a more important influence in determining the performance.The different behaviors of the secondary vortices explained the performance variations due to the clocking effect.

A power scalable PLL frequency synthesizer for high-speed Δ–Σ ADC

A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） or in low-power mode （35-130 MHz） to satisfy the ADC＇s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.