Cache performance optimization of irregular sparse matrix multiplication on modern multi-core CPU and GPU

This paper focuses on how to optimize the cache performance of sparse matrix-matrix multiplication(SpGEMM).It classifies the cache misses into two categories;one is caused by the irregular distribution pattern of the multiplier-matrix,and the other is caused by the multiplicand.For each of them,the paper puts forward an optimization method respectively.The first hash based method removes cache misses of the 1 st category effectively,and improves the performance by a factor of 6 on an Intel 8-core CPU for the best cases.For cache misses of the 2nd category,it proposes a new cache replacement algorithm,which achieves a cache hit rate much higher than other historical knowledge based algorithms,and the algorithm is applicable on CELL and GPU.To further verify the effectiveness of our methods,we implement our algorithm on GPU,and the performance perfectly scales with the size of on-chip storage.

Research on Multi-Core Processor Analysis for WCET Estimation

Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardware system.This literature review focuses on calculating WCET for multi-core processors,providing a survey of traditional methods used for static and dynamic analysis and highlighting the major challenges that arise from different program execution scenarios on multi-core platforms.This paper outlines the strengths and weaknesses of current methodologies and offers insights into prospective areas of research on multi-core analysis.By presenting a comprehensive analysis of the current state of research on multi-core processor analysis for WCET estimation,this review aims to serve as a valuable resource for researchers and practitioners in the field.

基于PCIe总线的主从CPU数据传输系统设计与实现

电力系统保护自动化设备存在多CPU板卡间高速数据传输和存储需求,介绍了一种基于PCIe总线接口实现的主从CPU数据传输系统。采用飞腾FT2000/4处理器为核心构建硬件系统,通过嵌入式Linux操作系统、PCIe设备驱动和应用程序部署软件系统,主CPU侧负责数据采集和处理,从CPU侧通过PCIe总线读取数据完成传输和存储功能。测试情况表明,该方案实现的系统稳定可靠,能够有效地满足高速传输、实时存储的应用业务需求,具有较高的工程应用价值。

面向多核CPU与GPU平台的图处理系统关键技术综述

图计算作为分析与挖掘关联关系的一种关键技术,已在智慧医疗、社交网络分析、金融反欺诈、地图道路规划、计算科学等领域广泛应用.当前,通用CPU与GPU架构的并行结构、访存结构、互连结构及同步机制的不断发展,使得多核CPU与GPU成为图处理加速的常用平台.但由于图处理具有处理数据规模大、数据依赖复杂、访存计算比高等特性,加之现实应用场景下的图数据分布不规则且图中的顶点与边呈现动态变化,给图处理的性能提升和高可扩展性带来严峻挑战.为应对上述挑战,大量基于多核CPU与GPU平台的图处理系统被提出,并在该领域取得显著成果.为了让读者了解多核CPU与GPU平台上图处理优化相关技术的演化,首先剖析了图数据、图算法、图应用特性,并阐明图处理所面临的挑战.然后分类梳理了当前已有的基于多核CPU与GPU平台的图处理系统,并从加速图处理设计的角度,详细、系统地总结了关键优化技术,包括图数据预处理、访存优化、计算加速和数据通信优化等.最后对已有先进图处理系统的性能、可扩展性等进行分析,并从不同角度对图处理未来发展趋势进行展望,希望对从事图处理系统研究的学者有一定的启发.

应用n-LSTM的云平台任务CPU负载预测方法

云平台任务的CPU负载预测有助于云平台资源的优化配置,以改善资源利用率.它是有效管理云资源的重要手段.为提高任务CPU负载预测精度,本文主要做了以下工作:1)利用热度图提取用于进行CPU负载预测的资源使用特征;2)设计并实现了一种基于n-LSTM的云平台任务的CPU负载预测方法DPFE-n-LSTM;3)分别在阿里云平台数据集和Google云平台数据集上进行了实验,结果表明,相对于目前已经提出的CPU负载预测模型BP、LSTM和CNN-LSTM,DPFE-n-LSTM方法具有更好的预测性能.

基于国产ARM架构CPU的导航卫星精密定轨解算效率优化方法

以国产飞腾CPU为例,讨论在国产ARM架构CPU基础上的导航卫星精密定轨解算效率优化方法。基于导航卫星精密定轨解算流程中钟差约化和法方程求逆耗时较多,分别利用多线程和OpenBlas对上述2个过程进行优化。结果表明,优化后解算效率大幅提升。钟差约化方面,采用100个测站32颗导航卫星进行解算时,原始单历元平均耗时1.105 s,优化后为0.188 s;法方程求逆方面,原始求逆平均耗时2 264 s,优化后仅需78 s。

Enrichment of Fetal Nucleated Red Blood Cells by Multi-core Magnetic Composite Particles for Non-invasive Prenatal Diagnosis

A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor（anti-CD71）, was prepared. The fetal nucleated red blood cells（FNRBCs） in the peripheral blood of a gravida were rapidly and effectively enriched and separated by the mo- dified multi-core magnetic composite particles in an external magnetic field. The obtained FNRBCs were used for the identification of the fetal sex by means of fluorescence in situ hybridization（FISH） technique. The results demonstrate that the multi-core magnetic composite particles meet the requirements for the enrichment and speration of FNRBCs with a low concentration and the accuracy of detetion for the diagnosis of fetal sex reached to 95%. Moreover, the obtained FNRBCs were applied to the non-invasive diagnosis of Down syndrome and chromosome 3p21 was de- tected. The above facts indicate that the novel multi-core magnetic composite particles-based method is simple, relia- ble and cost-effective and has opened up vast vistas for the potential application in clinic non-invasive prenatal diag- nosis.

基于MPI的鲲鹏CPU核间通信研究

核间通信延时是影响高性能计算系统整体运行效率的重要因素.国产鲲鹏CPU在高性能计算领域应用日益广泛,针对鲲鹏CPU的缓存架构及多核间接口互联进行分析,研究影响鲲鹏CPU核间通信延时的因素.在消息传递接口(MPI)环境下进行节点内核间通信实验,对包括跨三级缓存、跨物理CPU通信等不同模式下通信延时进行对比,发现通信数据包大于500 KB后,跨L3 Cache TAG的通信延时反优于共享L3 Cache TAG的通信延时.针对通信数据包在64 KB大小时的通信延迟异常,分析得出是MPI的Eager模式和Rendezvous模式的默认切换阈值所造成.对这两种模式进行实验对比,验证不同大小的通信数据包在不同模式下和跨核通信时的延时特征,Eager模式更适合低延时的小消息发送.在实际应用中可根据通信数据包大小调整两种模式的默认切换阈值,以达到更好的传输效果.实验结果表明由于鲲鹏CPU存在复杂的多核结构,在并行计算程序设计时可以进行针对性优化,以提升程序的运行效率.

CPU环境下多传感器数据融合的机器人3D目标检测方法

实时、准确的3D目标检测算法能提供目标的位置和形态信息,为移动机器人实现高效导航、有效避障等各项任务提供保障。现有的3D目标检测算法对硬件设备运算能力的依赖较为严重,为了在确保检测精度的同时降低方法对硬件设备的要求,提出一种能部署在移动机器人CPU环境下的多传感器融合3D目标检测方法。方法结合了2D目标检测和点云聚类技术,利用2D目标检测技术从图像中获取目标的检测信息,根据相机与雷达的空间映射关系对检测框内的点云进行分割,并对分割后的点云进行聚类和信息提取,从而实现3D目标的检测和定位功能。通过与经典的多传感器3D目标检测算法MVX-Net的对比,该算法有更优的检测精度,同时具有更小的计算复杂度。此外,该方法在实际移动机器人CPU设备的边缘终端上进行部署分析,算法的处理速度达到0.069s/帧,满足10Hz激光雷达频率的需求。

面向众核CPU的稠密线性求解器性能评测与优化

稠密线性求解器在高性能计算和机器学习等领域扮演着重要的角色。其典型的并行算法实现通常构建在著名的fork-join或task-based编程模型之上。尽管采用fork-join模型的主流稠密线性代数库能将大部分的计算转移到高度优化、高性能的BLAS 3例程上,由于fork-join不灵活的执行流,它们仍然未能高效地利用众核CPU的计算资源。采用task-based编程模型的开源库能实现更加灵活、负载更均衡的算法,因此能获得明显的性能提升。然而,在众核CPU平台上,尤其是对于中等矩阵规模的问题而言,它们仍然有较大的优化空间。对稠密线性求解器的性能进行了全面的测评,以定位性能瓶颈,并提出了2种优化策略,以提高程序性能。具体地,通过重叠LU分解和下三角求解的计算过程,减少同步开销线程的空等,从而提高算法的并行性;进一步通过减少冗余的矩阵打包操作,降低算法的访存开销。分别在2个主流的众核CPU平台(Intel®Xeon Gold®6252N(48核)和HiSilicon Kunpeng 920(64核))上进行了性能评估。实验结果表明,该优化的稠密线性求解器在上述两个CPU平台上,相比最佳开源实现分别取得了10.05%(Xeon)和13.63%(Kunpeng 920)的性能提升。

Variation-Aware Task Mapping on Homogeneous Fault-Tolerant Multi-Core Network-on-Chips

A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.

Multi-core optimization for conjugate gradient benchmark on heterogeneous processors

Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores.

Theoretical Analysis on Inter-Core Crosstalk Suppression Model for Multi-Core Fiber

Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so that the overlap of electric field distribution can be suppressed. We also propose approximate analytical solution(AAS) for κ of two crosstalk suppression models, which are two cores with one low index rod deployed in the middle and two cores with one low index rectangle trench deployed in the middle. We then do some modification for the results obtained by AAS and the modified results are proved to agree well with that obtained by finite element method(FEM). Therefore, we can use the modified AAS to get inter-core crosstalk for abovementioned two models quickly.

Parallel scheduling strategy of web-based spatial computing tasks in multi-core environment

In order to improve the concurrent access performance of the web-based spatial computing system in cluster,a parallel scheduling strategy based on the multi-core environment is proposed,which includes two levels of parallel processing mechanisms.One is that it can evenly allocate tasks to each server node in the cluster and the other is that it can implement the load balancing inside a server node.Based on the strategy,a new web-based spatial computing model is designed in this paper,in which,a task response ratio calculation method,a request queue buffer mechanism and a thread scheduling strategy are focused on.Experimental results show that the new model can fully use the multi-core computing advantage of each server node in the concurrent access environment and improve the average hits per second,average I/O Hits,CPU utilization and throughput.Using speed-up ratio to analyze the traditional model and the new one,the result shows that the new model has the best performance.The performance of the multi-core server nodes in the cluster is optimized;the resource utilization and the parallel processing capabilities are enhanced.The more CPU cores you have,the higher parallel processing capabilities will be obtained.

Modeling of Few-Mode Multi-Core Optical Fiber Channel Based on Non-Uniform Mode Field Distribution

In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are carried out and then the modeling scheme of few-mode multicore optical fiber channel based on non-uniform mode field distribution is put forward. The proposed modeling scheme can not only exponentially increases the system capacity through fewmode multi-core optical fiber channel, but has better transmission performance compared to the channel of the same type to the uniform channel revealing from the simulation results.

Hybridization of Metaheuristics Based Energy Efficient Scheduling Algorithm for Multi-Core Systems

The developments of multi-core systems(MCS)have considerably improved the existing technologies in thefield of computer architecture.The MCS comprises several processors that are heterogeneous for resource capacities,working environments,topologies,and so on.The existing multi-core technology unlocks additional research opportunities for energy minimization by the use of effective task scheduling.At the same time,the task scheduling process is yet to be explored in the multi-core systems.This paper presents a new hybrid genetic algorithm(GA)with a krill herd(KH)based energy-efficient scheduling techni-que for multi-core systems(GAKH-SMCS).The goal of the GAKH-SMCS tech-nique is to derive scheduling tasks in such a way to achieve faster completion time and minimum energy dissipation.The GAKH-SMCS model involves a multi-objectivefitness function using four parameters such as makespan,processor utilization,speedup,and energy consumption to schedule tasks proficiently.The performance of the GAKH-SMCS model has been validated against two datasets namely random dataset and benchmark dataset.The experimental outcome ensured the effectiveness of the GAKH-SMCS model interms of makespan,pro-cessor utilization,speedup,and energy consumption.The overall simulation results depicted that the presented GAKH-SMCS model achieves energy effi-ciency by optimal task scheduling process in MCS.

Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture

Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in multi-core processors.

MQTT物联网平台在国产申威CPU平台上的移植部署

当前国产芯片正在得到大力的推广,国产芯片软件生态也在迅速建设中,文章围绕开源MQTT服务软件在国产申威CPU平台的移植、部署、测试应用,主要讨论MQTT协议以及基于国产申威CPU平台移植部署MQTT服务器的方法,移植完成后通过基于国产CPU服务器搭建物联网平台进行测试,测试系统采用B/S系统架构,实现了多个客户端之间通过MQTT服务实现数据的交换。目的在于推广基于国产芯片的国产软件生态建设,让更多的人参与到国产芯片的软件生态建设中,有利于积极推进各种软件项目从底层到应用层的国产化发展,为信创国产化事业添砖加瓦。

Performance Behaviour Analysis of the Present 3-Level Cache System for Multi-Core Processors

In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core processors is developed and its possible performance has been analyzed with the increase in number of cores. Various important performance parameters like access time and utilization of individual cache at different level and overall average access time of the cache system is determined. Results for up to 1024 cores have been reported in this paper.

Performance Analysis for EDMA Based on TIC6678Multi-core DSP

Frequent data exchange among all kinds of memories has become an inevitable phenomenon in the process of modern embeddedsoftware design. In order to improve the ability of the embedded system data＇s throughput and computation, most embeddeddevices introduce Enhanced Direct Memory Access （EDMA） data transfer technology. TMS320C6678 is a multi-core DSPproduced by Texas Instruments （TI）. There are ten EDMA transmission controllers in the chip for configuration and datatransmissions are allowed to be performed between any two pieces of storage at the same time. This paper expounds the workingmechanism of EDMA based on multi-core DSP TMS320C6678. At the same time, multiple data sets are provided and thebottleneck of limiting data throughout is analyzed and solved.