Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.

DESIGN OF TERNARY CURRENT-MODE CMOS CIRCUITS BASED ON SWITCH-SIGNAL THEORY

By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.

SYNTHESIS OF MULTIVALUED CMOS CIRCUITS WITH MANY VARIABLES BASED ON TRANSMISSION FUNCTION THEORY

Based on transmission function theory,the synthesis technique for multivaluedCMOS circuits is discussed.By comparing the CMOS circuits based on transmission functiontheory with the T gate,it is shown that their action principles are identical.Based on it,thesynthesis method for multivalued CMOS circuits with many variables by using function decom-position is proposed.

SIMPLIFICATION OF CURRENT-MODE MULTIVALUED CMOS CIRCUITS

This paper proposes a simplification method for realization of current-mode multivalued CMOS circuits. The key of this method is to find a cover on the K-map for a given multivalued function, which fits to the realization of current-mode CMOS circuits. The design example shows that the design presented in this paper is better than the design proposed by G. W. Dueck et al. (1987).

DESIGN OF SYMMETRIC TERNARY CURRENT-MODE CMOS CIRCUITS

By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.

A review on the design of ternary logic circuits

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

Design of Multi-Valued Logic Circuit Using Carbon Nano Tube Field Transistors

The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.

A Comparative Study of Majority/Minority Logic Circuit Synthesis Methods for Post-CMOS Nanotechnologies

The physical limitations of complementary metal-oxide semiconductor?(CMOS) technology have led many researchers to consider other alternative technologies. Quantum-dot cellular automate (QCA), single electron tunneling (SET), tunneling phase logic (TPL), spintronic devices, etc., are some of the nanotechnologies that are being considered as possible replacements for CMOS. In these nanotechnologies, the basic logic units used to implement circuits are majority and/or minority gates. Several majority/minority logic circuit synthesis methods have been proposed. In this paper, we give a comparative study of the existing majority/minority logic circuit synthesis methods that are capable of synthesizing multi-input multi-output Boolean functions. Each of these methods is discussed in detail. The optimization priorities given to different factors such as gates, levels, inverters, etc., vary with technologies. Based on these optimization factors, the results obtained from different synthesis methods are compared. The paper also analyzes the optimization capabilities of different methods and discusses directions for future research in the synthesis of majority/minority logic networks.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock gen- erator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks—Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor (NMOS) and Complementary Metal Oxide Semiconductor (CMOS) latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company (TSMC) 0.25μm CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic (BCRL) and Pass-transistor Adiabatic Logic (PAL) including their clock generators is simulated. The simula-tion result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.

Two Analytical Methods for Detection and Elimination of the Static Hazard in Combinational Logic Circuits

In this paper, the authors continue the researches described in [1], that consists in a comparative study of two methods to eliminate the static hazard from logical functions, by using the form of Product of Sums (POS), static hazard “0”. In the first method, it used the consensus theorem to determine the cover term that is equal with the product of the two residual implicants, and in the second method it resolved a Boolean equation system. The authors observed that in the second method the digital hazard can be earlier detected. If the Boolean equation system is incompatible (doesn’t have solutions), the considered logical function doesn’t have the static 1 hazard regarding the coupled variable. Using the logical computations, this method permits to determine the needed transitions to eliminate the digital hazard.

QUATERNARY CMOS CIRCUITS BASED ON TRANSMISSION FUNCTION THEORY

The transmission function theory is proposed, the quaternary and logic variables are distinguished, and three kinds of new operations (i.e. the threshold comparison operation, transmission operation and union operation) are introduced. Since these operations describe the action principle of metal-oxide semiconductor (MOS) transistors, the transmission functions expressed by using them and logic operations can direct the realization of quaternary complementary metal-oxide semiconductor (CMOS) circuits. In this paper the design of CMOS circuits for some basic transmission functions is proposed. The computer simulation has confirmed that these circuits have correct logic and desirable DC transfer characteristics. Furthermore, the synthesis technique for a quaternary CMOS transmission network is also proposed here.

TWO-INPUT PRESETTING TECHNIQUE AND DESIGN OF CMOS FLIP-FLOPS WITH A HIGH RADIX

By analysing the difficulty of previous flip-flops with a high radix, this paper proposes a logic design scheme with two presetting inputs. The circuit of a quaternary CMOS flip-flop is designed by using the transmission function theory. The result shows that its structure is simpler and its processing speed is higher than that of two binary flip-flops which store the equal information.

LOGICAL SYNTHESIS OF MOLTIVALUED SYMMETRIC FUNCTION BASED ON BINARY FULL ADDERS

This paper discusses the definition and properties of multivalued symmetric functions, points out that a multivalued symmetric function can be decomposed according to the value of the function j. The subfunction Lj corresponding to j must be a symmetric function, and it may be expressed as the sum of products form of degenerated multivalued fundamental symmetric functions. Based on this consideration, the circuit realization for the multivalued symmetric functions based on full adders is proposed.

A UNIFIED THEORY FOR DESIGNING ANDANALYZING BOTH SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.

CircuitVerse:A Simulator for Teaching and Learning of Digital Logic Circuit

Digital Logic is a fundamental course of majors in electronic information.The simulation experiment is an essential measure to help students understand the principles of digital logic.It can improve the efficiency of physical experiments and decrease instrument damage caused by operating errors.CircuitVerse is an open-source and Web-based tool of circuit design and simulation for teaching purposes.And now,teachers and students in many colleges and universities use it to assist teaching and learning.Firstly,through a particular example,the features of CircuitVerse and its usage are explained.Secondly,we briefly introduce the application of CircuitVerse in our teaching as well as the following development plans.We believe that our introduction can help teachers understand the software and how to make full use of this tool.

Logical Function Decomposition Method for Synthesis of Digital Logical System Implemented with Programmable Logic Devices (PLD)

The paper consists in the use of some logical functions decomposition algorithms with application in the implementation of classical circuits like SSI, MSI and PLD. The decomposition methods use the Boolean matrix calculation. It is calculated the implementation costs emphasizing the most economical solutions. One important aspect of serial decomposition is the task of selecting “best candidate” variables for the G function. Decomposition is essentially a process of substituting two or more input variables with a lesser number of new variables. This substitutes results in the reduction of the number of rows in the truth table. Hence, we look for variables which are most likely to reduce the number of rows in the truth table as a result of decomposition. Let us consider an input variable purposely avoiding all inter-relationships among the input variables. The only available parameter to evaluate its activity is the number of “l”s or “O”s that it has in the truth table. If the variable has only “1” s or “0” s, it is the “best candidate” for decomposition, as it is practically redundant.

基于相关性分离的逻辑电路敏感门定位算法

随着CMOS器件特征尺寸进入纳米量级,因高能粒子辐射等造成的电路失效问题日益严重,给电路可靠性带来严峻挑战。现阶段,准确评估集成电路可靠性,并以此为依据对电路进行容错加固,以提高电路系统可靠性变得刻不容缓。然而,由于逻辑电路中存在大量扇出重汇聚结构,由此引发的信号相关性导致可靠性评估与敏感单元定位面临困难。该文提出一种基于相关性分离的逻辑电路敏感门定位算法。先将电路划分为多个独立电路结构(ICS);以ICS为基本单元分析故障传播及信号相关性影响;再利用相关性分离后的电路模块和反向搜索算法精准定位逻辑电路敏感门单元;最后综合考虑面向输入向量空间的敏感门定位及针对性容错加固。实验结果表明,所提算法能准确、高效地定位逻辑电路敏感单元,适用于大规模及超大规模电路的可靠性评估与高效容错设计。

基于并联开关的低电压低功耗电流型CMOS电路设计

该文提出了一种电流型CMOS电路的并联开关结构,使得电流型CMOS电路能在较低的电源电压下工作,因而可以实现电路的低功耗设计,同时在相同的电源电压下,采用并联开关结构的电路比相应的串联开关电路具有更快的速度.PSPICE模拟证明了采用并联开关结构设计的电路能在较低的电源电压下工作,并具有较小的电路延时.