New CMOS compatible super-junction LDMOST with n-type buried layer

A new super-junction lateral double diffused MOSFET （LDMOST） structure is designed with n-type charge compensation layer embedded in the p^--substrate near the drain to suppress substrate-assisted depletion effect that results from the compensating charges imbalance between the pillars in the n-type buried layer. A high electric field peak is introduced in the surface by the pn junction between the p^--substrate and n-type buried layer, which given rise to a more uniform surface electric field distribution by modulation effect. The effect of reduced bulk field （REBULF） is introduced to improve the vertical breakdown voltage by reducing the high bulk electric field around the drain, The new structure features high breakdown voltage, low on-resistance and charges balance in the drift region due to n-type buried layer.

A high voltage Bi-CMOS compatible buffer super-junction LDMOS with an N-type buried layer

A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.

Synergistic Optimization of Buried Interface by Multifunctional Organic-Inorganic Complexes for Highly Efficient Planar Perovskite Solar Cells

For the further improvement of the power conversion efficiency(PCE)and stability of perovskite solar cells(PSCs),the buried interface between the perovskite and the electron transport layer is crucial.However,it is challenging to effectively optimize this interface as it is buried beneath the perovskite film.Herein,we have designed and synthesized a series of multifunctional organic-inorganic(OI)complexes as buried interfacial material to promote electron extraction,as well as the crystal growth of the perovskite.The OI complex with BF4−group not only eliminates oxygen vacancies on the SnO_(2) surface but also balances energy level alignment between SnO_(2) and perovskite,providing a favorable environment for charge carrier extraction.Moreover,OI complex with amine(−NH_(2))functional group can regulate the crystallization of the perovskite film via interaction with PbI2,resulting in highly crystallized perovskite film with large grains and low defect density.Consequently,with rational molecular design,the PSCs with optimal OI complex buried interface layer which contains both BF4−and−NH_(2) functional groups yield a champion device efficiency of 23.69%.More importantly,the resulting unencapsulated device performs excellent ambient stability,maintaining over 90%of its initial efficiency after 2000 h storage,and excellent light stability of 91.5%remaining PCE in the maximum power point tracking measurement(under continuous 100 mW cm−2 light illumination in N2 atmosphere)after 500 h.

Buried straw layer and plastic mulching increase microflora diversity in salinized soil

Salt stress has been increasingly constraining crop productivity in arid lands of the world. In our recent study, salt stress was aleviated and crop productivity was improved remarkably by straw layer burial plus plastic iflm mulching in a saline soil. However, its impact on the microlfora diversity is not wel documented. Field micro-plot experiments were conducted from 2010 to 2011 using four tilage methods： （i） deep tilage with plastic iflm mulching （CK）, （i） straw layer burial at 40 cm （S）, （ii） straw layer burial plus surface soil mulching with straw material （S＋S）, and （iv） plastic iflm mulching plus buried straw layer （P＋S）. Culturable microbes and predominant bacterial communities were studied; based on 16S rDNA, bacterial com-munity structure and abundance were characterized using denaturing gradient gel electrophoresis （DGGE） and polymerase chain reaction （PCR）. Results showed that P＋S was the most favorable for culturable bacteria, actinomyces and fungi and induced the most diverse genera of bacteria compared to other tilage methods. Soil temperature had signiifcant positive correlations with the number of bacteria, actinomyces and fungi （P〈0.01）. However, soil water was poorly correlated with any of the microbes. Salt content had a signiifcant negative correlation with the number of microbers, especialy for bacteria and fungi （P〈0.01）. DGGE analysis showed that the P＋S exhibited the highest diversity of bacteria with 20 visible bands folowed by S＋S, S and CK. Moreover, P＋S had the highest similarity （68%） of bacterial communities with CK. The major bacterial genera in al soil samples wereFirmicutes,Proteobacteria andActinobacteria. Given the considerable increase in microbial growth, the combined use of straw layer burial and plastic iflm mulching could be a practical option for aleviating salt stress effects on soil microbial community and thereby improving crop production in arid saline soils.

A novel high performance TFS SJ IGBT with a buried oxide layer

A novel high performance trench field stop （TFS） superjunction （S J） insulated gate bipolar transistor （IGBT） with a buried oxide （BO） layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT （Conv-SJ）, the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop （gce（on）） and an improved tradeoff between gee（on） and turn-off loss （Eoff）, with no breakdown voltage （BV） degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5μm and Nn = Np = 3 × 10^15 cm^-3, the Vce（on） and Eoff of the proposed structure are 1.08 V and 2.81 mJ/cm2 with the collector doping concentration Nc = 1 × 10^18 cm^-3 and 1.12 V and 1.73 mJ/cm2 with Nc = 5 × 10^17 cm^-3, respectively. However, with the same device parameters, the Vce（on） and Eoff for the Conv-SJ are 1.81 V and 2.88 mJ/cm2 with Nc= 1 × 10^18 cm^-3 and 1.98 V and 2.82 mJ/cm2 with Nc = 5 ×10^17 cm^-3, respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.

Enhancement of Breakdown Voltage in AlGaN/GaN High Electron Mobility Transistors Using Double Buried p-Type Layers

A novel A1GaN/GaN high electron mobility transistor （HEMT） with double buried p-type layers （DBPLs） in the GaN buffer layer and its mechanism are studied. The DBPL A1GaN/GaN HEMT is characterized by two equi-long p-type GaN layers which are buried in the GaN buffer layer under the source side. Under the condition of high-voltage blocking state, two reverse p-n junctions introduced by the buried p-type layers will effectively modulate the surface and bulk electric fields. Meanwhile, the buffer leakage is well suppressed in this structure and both lead to a high breakdown voltage. The simulations show that the breakdown voltage of the DBPL structure can reach above 2000 V from 467 V of the conventional structure with the same gate-drain length of 8μm.

A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through（LPT） carrier stored trench bipolar transistor（CSTBT） with buried p-layer（BP） is proposed in this paper.Since the negative charges in the BP layer modulate the bulk electric field distribution,the electric field peaks both at the junction of the p base/n-type carrier stored（N-CS） layer and the corners of the trench gates are reduced,and new electric field peaks appear at the junction of the BP layer/N drift region.As a result,the overall electric field in the N drift region is enhanced and the proposed structure improves the breakdown voltage（BV） significantly compared with the LPT CSTBT.Furthermore,the proposed structure breaks the limitation of the doping concentration of the N-CS layer（NN CS） to the BV,and hence a higher NN CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop（Vce（sat）） can be obtained with almost constant BV.The results show that with a BP layer doping concentration of NBP = 7 × 10^15 cm^-3,a thickness of LBP = 2.5 μm,and a width of WBP = 5 μm,the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V,with NN CS increasing from 5 × 10^15 cm^-3 to 2.5 × 10^16 cm^-3.However,with the same N-drift region thickness of 150 μm and NN CS,the BV of the CSTBT decreases from 1598 V to 247 V.Meanwhile,the Vce（sat） of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN CS increasing from 5 × 10^15 cm^-3 to 2.5 × 10^16 cm^-3.

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator （SOI） high performance lateral double-diffusion metal oxide semiconductor （LDMOS） on a compound buried layer （CBL） with a step buried oxide （SBO CBL SOI） is proposed. The step buried oxide locates holes in the top interface of the upper buried oxide （UBO） layer. Furthermore, holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide （LBO） layer. Consequently, the electric fields in both the thin LBO and the thick UBO are enhanced by these holes, leading to an improved breakdown voltage. The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer. Moreover, SBO CBL SOI can also reduce the self-heating effect.

A novel structure of a high current gain 4H-SiC BJT with a buried layer in the base

In this paper, a new structure of a 4H-SiC bipolar junction transistor （BJT） with a buried layer （BL） in the base is presented. The current gain shows an approximately 100% increase compared with that of the conventional structure. This is attributed to the creation of a built-in electric field for the minority carriers to transport in the base which is explained based on 2D device simulations. The optimized design of the buried layer region is also considered by numeric simulations.

OPTICAL EFFECTS AND MICROSTRUCTURE OF BURIED INSULATOR LAYER FORMED BY O^+ AND N^+ CO-IMPLANTATION

The microstructure and optical properties of a buried layer formed by O+(200keV,1.8×1018/cm2)and N+(180 keV,4×1017/cm2)co-implantation and annealed at 1200℃for 2 h have been investigated by Auger electron,IR absorption and reflection spectroscopicmeasurements.The results show that the buried layer consists of silicon dioxide and SiOx（x【 2）and the nitrogen segregates to the wings of the buried layer where it forms an oxynitride.Bydetail theoretical analysis and computer simulation of the IR reflection interference spectrum,therefractive index profiles of the buried layer were obtained.

Novel fast-switching LIGBT with P-buried layer and partial SOI

A novel silicon-on-insulator lateral insulated gate bipolar transistor(SOI LIGBT)is proposed in this paper.The proposed device has a P-type buried layer and a partial-SOI layer,which is called the BPSOI-LIGBT.Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer,the proposed structure generates two new peaks in the surface electric field distribution,which can achieve a smaller device size with a higher breakdown voltage.The smaller size of the device is beneficial to the fast switching.The simulation shows that under the same size,the breakdown voltage of the BPSOI LIGBT is 26%higher than that of the conventional partial-SOI LIGBT(PSOI LIGBT),and 84%higher than the traditional SOI LIGBT.When the forward voltage drop is 2.05 V,the turn-off time of the BPSOI LIGBT is 71%shorter than that of the traditional SOI LIGBT.Therefore,the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT.In addition,the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.

Visual field defects and retinal nerve fiber layer damage in buried optic disc drusen: a new insight

AIM: To assess the association between buried optic disc drusen(BODD) location using spectral-domain optical coherence tomography(SD-OCT) and the location of associated visual field defects(VFD) using the Garway-Heath mapping.METHODS: This monocentric retrospective crosssectional study was led at the authors’ institution. Adult patients diagnosed with BODD who had complete records with a reliable Humphrey? 24-2 visual field, macular, and papillary OCT were enrolled. Fisher’s exact test was used to measure the association between BODD location and VFD distribution according to Garway-Heath’s mapping.RESULTS: Totally 20 eyes of 15 patients were included(60% females). The median age(interquartile range) was 63(43)y and the median best corrected visual acuity(BCVA) was-0.08(0.08) log MAR. BODD were mostly located in zones A, E, and F. The minimal rim width(MRW) was globally preserved. The retinal nerve fiber layer(RNFL) was predominantly altered in zones D, E, and F. There was a significant correlation between BODD location and that of RNFL alterations in zones D(P=0.03) and E(P=0.025);Moreover, the presence of BODD in the E zone was significantly related to damaged RNFL in the neighbouring sectors D and F(P=0.012;P=0.02 respectively). Sixty-three percent(12/19) of visual fields were abnormal and there was a significant match(Phi=0.7, P=0.009) between drusen location and VFD only in zone D.CONCLUSION: BODD do not only affect young patients and can be more harmful than usually expected, as we found VFD in 63% of cases. There is a correspondence between BODD location, RNFL damage, and VFD distributions. The presence of BODD induces the overestimation of MRW,thereby disrupting its sensitivity as an early indicator of ganglion fibers damage.

Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and Al2O3 Dielectric

Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel lateral double-diffused metal–oxide semiconductor（LDMOS） with a high breakdown voltage（BV） and low specific on-resistance（Ron.sp） is proposed and investigated by simulation. It features a junction field plate（JFP） over the drift region and a partial N-buried layer（PNB） in the P-substrate. The JFP not only smoothes the surface electric field（E-field）, but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%,and a reduction in Ron.sp by 45.7% simultaneously.

INCREASING BREAKDOWN VOLTAGE OF LDMOST USING BURIED LAYER

A new LDMOST structure, named B-LDMOST that has a buried layer under the drain is proposed. The buried layer is not connected to the drift region, so it can optimize the vertical field distribution and increase breakdown voltage. The analysis and the simulated results show that B-LDMOST can increase breakdown voltage, with almost negligible influence on the other parameters such as on-resistance, switching time, and so on.

Seismic Waves in a Layered Half-Space from an Arbitrary Buried Source

In this paper, a transfer matrix and a three-dimensional dynamic response of a layered half-space to an arbitrary buried source are derived with the aid of a technique which combines the Laplace and two-dimensional Fourier transforms in a rectangular coordinate system. This method is clear in concept, and the corresponding formulas given in the paper are simple and convenient for marine seismic prospecting and other fields' applications. An example is presented and the calculated results are in good agreement with those of the finite element method (FEM).

Study on Electrical Potential by Buried Source Electrode within the Horizontally Layered Half-space Model

The paper first studies the analytical expression of electrical potential by a point current source in a uniform half-space medium,and then focuses on the distribution of electrical potential in a horizontally layered half-space model by a point current source within the surface layer or the bottom layer.Finally,the electrical potential by a source electrode in any layer of a layered half-space model is presented.

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance （Ron,sp） adaptive buried electrode （ABE） silicon-on-insulator （SOI） power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide （BOX） layer, the negative drain voltage Vd is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than tile electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field EI and the breakdown voltage （BV） of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low Ron,sp is obtained. Furthermore, the structure also alleviates the self-heating effect （SHE）. The analytical model matches the simulation results.

An electrochemical method for evaluating the resistance to cathodic disbondment of anti-corrosion coatings on buried pipelines

Methods for evaluating the resistance to cathodic disbondment （RCD） of anti-corrosion coatings on buried pipelines were reviewed. It is obvious that these traditional cathodic disbondment tests （CDT） have some disadvantages and the evaluated results are only simple figures and always rely on the subjective experience of the operator. A new electrochemical method for evaluating the RCD of coatings, that is, the potentiostatic evaluation method （PEM）, was developed and studied. During potentiostatic anodic polarization testing, the changes of stable polarization current of specimens before and after cathodic disbonding （CD） were measured, and the degree of cathodic disbondment of the coating was quantitatively evaluated, among which the equivalent cathodic disbonded distance AD was suggested as a parameter for evaluating the RCD. A series of testing parameters of the PEM were determined in these experiments.

A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

A novel low specific on-resistance （Ron,sp） silicon-on-insulator （SO1） p-channel lateral double-diffused metal-oxide semiconductor （pLDMOS） compatible with high voltage （HV） n-channel LDMOS （nLDMOS） is proposed. The pLDMOS is built in the N-type SO1 layer with a buried P-type layer acting as a current conduction path in the on-state （BP SOl pLD- MOS）. Its superior compatibility with the HV nLDMOS and low voltage （LV） complementary metal-oxide semiconductor （CMOS） circuitry which are formed on the N-SOl layer can be obtained. In the off-state the P-buried layer built in the NSOI layer causes multiple depletion and electric field reshaping, leading to an enhanced （reduced） surface field （RESURF） effect. The proposed BP SO1 pLDMOS achieves not only an improved breakdown voltage （BV） but also a significantly reduced Ron,sp. The BV of the BP SO1 pLDMOS increases to 319 V from 215 V of the conventional SO1 pLDMOS at the same half cell pitch of 25 μm, and Ron,sp decreases from 157 mΩ.cm2 to 55 mΩ.cm2. Compared with the PW SO1 pLDMOS, the BP SO1 pLDMOS also reduces the Ron,sp by 34% with almost the same BV.