In this paper we proposed a new design for all optical NAND gate.By combining nonlinear Kerr effect with photonic crystal ring resonators,we designed an all optical NAND gate.A typical NAND gate is a logic device with...In this paper we proposed a new design for all optical NAND gate.By combining nonlinear Kerr effect with photonic crystal ring resonators,we designed an all optical NAND gate.A typical NAND gate is a logic device with one bias and two logic input and one output ports.It has four different combinations for its logic input ports.The output port of the NAND gate is OFF,when both logic ports are ON,otherwise the output port will be ON.The switching power threshold obtained for this structure equals to 1.5 kW/lm2.For designing the proposed optical logic gate we employed one resonant ring whose resonant wavelength is at 1554 nm.The functionality of the proposed NAND gate depends on the operation of this resonant ring.When the power intensity of optical waves is less than the switching threshold the ring will couple optical waves into drop waveguide otherwise the optical waves will propagate on the bus waveguide.展开更多
The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tu...The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10^(18) cm^(-3) and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.展开更多
In order to make systems that are based on unreliable components reliable, the design of fault tolerant architectures will be necessary. Inspired by von Neumann＇s negative AND（NAND）multiplexing and William＇s inter...In order to make systems that are based on unreliable components reliable, the design of fault tolerant architectures will be necessary. Inspired by von Neumann＇s negative AND（NAND）multiplexing and William＇s interwoven redundant logic, this paper presents a fault tolerant technique based on redundancy-modified NAND gates for future nanocomputers. Bifurcation theory is used to analyze fault tolerant ability of the system and the simulation results show that the new system has a much higher fault tolerant ability than the conventional multiplexing based on NAND gates.According to the evaluation, the proposed architecture can tolerate a device error rate of up to 10-1, with multiple redundant components. This fault tolerant technique is potentially useful for future nanoelectronics.展开更多
基金This work has been supported by Young Researchers and Elite Club,Ahar Branch,Islamic Azad University,Ahar,Iran.
文摘In this paper we proposed a new design for all optical NAND gate.By combining nonlinear Kerr effect with photonic crystal ring resonators,we designed an all optical NAND gate.A typical NAND gate is a logic device with one bias and two logic input and one output ports.It has four different combinations for its logic input ports.The output port of the NAND gate is OFF,when both logic ports are ON,otherwise the output port will be ON.The switching power threshold obtained for this structure equals to 1.5 kW/lm2.For designing the proposed optical logic gate we employed one resonant ring whose resonant wavelength is at 1554 nm.The functionality of the proposed NAND gate depends on the operation of this resonant ring.When the power intensity of optical waves is less than the switching threshold the ring will couple optical waves into drop waveguide otherwise the optical waves will propagate on the bus waveguide.
基金Project supported by the San Disk Info Tech Shanghai,Chinathe Institute of Microelectronic Materials&Technology,School of Materials Science and Engineering,Shanghai Jiao Tong University,China。
文摘The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10^(18) cm^(-3) and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.
基金supported by the National Natural Science Foundation of China(61571149)
文摘In order to make systems that are based on unreliable components reliable, the design of fault tolerant architectures will be necessary. Inspired by von Neumann＇s negative AND（NAND）multiplexing and William＇s interwoven redundant logic, this paper presents a fault tolerant technique based on redundancy-modified NAND gates for future nanocomputers. Bifurcation theory is used to analyze fault tolerant ability of the system and the simulation results show that the new system has a much higher fault tolerant ability than the conventional multiplexing based on NAND gates.According to the evaluation, the proposed architecture can tolerate a device error rate of up to 10-1, with multiple redundant components. This fault tolerant technique is potentially useful for future nanoelectronics.
