In general, NAND flash memory has advantages in low power consumption, storage capacity, and fast erase/write performance in contrast to NOR flash. But, main drawback of the NAND flash memory is the slow access time f...In general, NAND flash memory has advantages in low power consumption, storage capacity, and fast erase/write performance in contrast to NOR flash. But, main drawback of the NAND flash memory is the slow access time for random read operations. Therefore, we proposed the new NAND flash memory package for overcoming this major drawback. We present a high performance and low power NAND flash memory system with a dual cache memory. The proposed NAND flash package consists of two parts, i.e., an NAND flash memory module, and a dual cache module. The new NAND flash memory system can achieve dramatically higher performance and lower power consumption compared with any conventionM NAND-type flash memory module. Our results show that the proposed system can reduce about 78% of write operations into the flash memory cell and about 70% of read operations from the flash memory cell by using only additional 3KB cache space. This value represents high potential to achieve low power consumption and high performance gain.展开更多
Based on the analysis of typical hybrid-type content addressable memory （CAM） structures, a hybrid-type CAM architecture with lower power consumption and higher stability was proposed. This design changes the connec...Based on the analysis of typical hybrid-type content addressable memory （CAM） structures, a hybrid-type CAM architecture with lower power consumption and higher stability was proposed. This design changes the connection of a N-type metal-oxide-semiconductor （NMOS） transistor in the control circuit, which greatly reduces the power consumption during comparison by making the match line simply discharge to the NMOS threshold voltage. A comparative study was made between conventional and the proposed hybrid-type CAM architecture by semiconductor manufacturing international corporation （SMIC） 65 nm complementary metal-oxide-semiconductor （CMOS） technology. Simulation shows that the power consumption of the proposed structure is reduced by 23%. Furthermore, the proposed design also adjusts the match line （ML） discharge path. In case that, the not and type （NAND-type） block is matched and the not or type （NOR-type） block is mismatched, the jitter voltage on the match line can be decreased largely.展开更多
基金This work was supported by Korea Research Foundation Grant funded by Korea Government(MOEHRD,Basic Research Promotion Fund)(Grant No.KRF-2005-003-D00270).
文摘In general, NAND flash memory has advantages in low power consumption, storage capacity, and fast erase/write performance in contrast to NOR flash. But, main drawback of the NAND flash memory is the slow access time for random read operations. Therefore, we proposed the new NAND flash memory package for overcoming this major drawback. We present a high performance and low power NAND flash memory system with a dual cache memory. The proposed NAND flash package consists of two parts, i.e., an NAND flash memory module, and a dual cache module. The new NAND flash memory system can achieve dramatically higher performance and lower power consumption compared with any conventionM NAND-type flash memory module. Our results show that the proposed system can reduce about 78% of write operations into the flash memory cell and about 70% of read operations from the flash memory cell by using only additional 3KB cache space. This value represents high potential to achieve low power consumption and high performance gain.
基金supported by the Natural Science Fund for Colleges and Universities in Anhui Province (KJ2013A006)
文摘Based on the analysis of typical hybrid-type content addressable memory （CAM） structures, a hybrid-type CAM architecture with lower power consumption and higher stability was proposed. This design changes the connection of a N-type metal-oxide-semiconductor （NMOS） transistor in the control circuit, which greatly reduces the power consumption during comparison by making the match line simply discharge to the NMOS threshold voltage. A comparative study was made between conventional and the proposed hybrid-type CAM architecture by semiconductor manufacturing international corporation （SMIC） 65 nm complementary metal-oxide-semiconductor （CMOS） technology. Simulation shows that the power consumption of the proposed structure is reduced by 23%. Furthermore, the proposed design also adjusts the match line （ML） discharge path. In case that, the not and type （NAND-type） block is matched and the not or type （NOR-type） block is mismatched, the jitter voltage on the match line can be decreased largely.
