An empirical expression for the direct tunneling (DT) current is obtained.This expression can be used to calculate the DT current for nMOSFETs with ultra thin oxide when the oxide thickness is considered as an adjust...An empirical expression for the direct tunneling (DT) current is obtained.This expression can be used to calculate the DT current for nMOSFETs with ultra thin oxide when the oxide thickness is considered as an adjustable parameter.The results have good agreement with the experimental data.And the oxide thickness obtained is less than the value acquired from the capacitance voltage( C V )method.展开更多
This paper presents the fabrication and performance of a 0.18μm nMOSFET for RF applications. This device features a nitrided oxide/poly-silicon gate stack, a lightly-doped-drain source/drain extension, a retrograde c...This paper presents the fabrication and performance of a 0.18μm nMOSFET for RF applications. This device features a nitrided oxide/poly-silicon gate stack, a lightly-doped-drain source/drain extension, a retrograde channel doping profile, and a multiple-finger-gate layout,each of which is achieved with conventional semiconductor fabrication facilities. The 0.18μm gate length is obtained by e-beam direct-writing. The device is fabricated with a simple process flow and exhibits excellent DC and RF performance： the threshold voltage of 0.52V, the sub-threshold swing of 80mV/dec, the drain-induced-barrier-lowering factor of 69mV/V, the off-state current of 0.5nA/μm, the saturation drive current of 458μA/μm （for the 6nm gate oxide and the 3V supply voltage）, the saturation transconductance of 212μS/μm,and the cutoff frequency of 53GHz.展开更多
A novel Schottky body-contacted structure for partially depleted SOI nMOSFET's is presented.This structure can be realized by forming a shallow n +-p junction and two sidewall spacers in the source region,and the...A novel Schottky body-contacted structure for partially depleted SOI nMOSFET's is presented.This structure can be realized by forming a shallow n +-p junction and two sidewall spacers in the source region,and then growing a thick silicide film,which can punch through the shallow junction and make a Schottky contact to the p-type silicon.Simulation results show that the anomalous subthreshold slope and kink effects are suppressed successfully and the drain breakdown voltage is improved considerably.This method has the same device area and is completely compatible with the bulk MOSFET process.展开更多
Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrie...Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrier effect （HCE） has also been proven to be very weak. In this paper, the reason why the annular gate nMOSFETs have good TID but bad HCE resistance is discussed in detail, and an improved design to locate the source contacts only along one side of the annular gate is used to weaken the HCE degradation. The good TID and HCE hardened capability of the design are verified by the experiments for I/O and core nMOSFETs in a 0.18 μm bulk CMOS technology. In addition, the shortcoming of this design is also discussed and the TID and the HCE characteristics of the replacers （the annular source nMOSFETs） are also studied to provide a possible alternative for the designers.展开更多
文摘An empirical expression for the direct tunneling (DT) current is obtained.This expression can be used to calculate the DT current for nMOSFETs with ultra thin oxide when the oxide thickness is considered as an adjustable parameter.The results have good agreement with the experimental data.And the oxide thickness obtained is less than the value acquired from the capacitance voltage( C V )method.
文摘This paper presents the fabrication and performance of a 0.18μm nMOSFET for RF applications. This device features a nitrided oxide/poly-silicon gate stack, a lightly-doped-drain source/drain extension, a retrograde channel doping profile, and a multiple-finger-gate layout,each of which is achieved with conventional semiconductor fabrication facilities. The 0.18μm gate length is obtained by e-beam direct-writing. The device is fabricated with a simple process flow and exhibits excellent DC and RF performance： the threshold voltage of 0.52V, the sub-threshold swing of 80mV/dec, the drain-induced-barrier-lowering factor of 69mV/V, the off-state current of 0.5nA/μm, the saturation drive current of 458μA/μm （for the 6nm gate oxide and the 3V supply voltage）, the saturation transconductance of 212μS/μm,and the cutoff frequency of 53GHz.
文摘A novel Schottky body-contacted structure for partially depleted SOI nMOSFET's is presented.This structure can be realized by forming a shallow n +-p junction and two sidewall spacers in the source region,and then growing a thick silicide film,which can punch through the shallow junction and make a Schottky contact to the p-type silicon.Simulation results show that the anomalous subthreshold slope and kink effects are suppressed successfully and the drain breakdown voltage is improved considerably.This method has the same device area and is completely compatible with the bulk MOSFET process.
基金supported by the Key Program of the National Natural Science Foundation of China(Grant No.60836004)the National Natural Science Foundation of China(Grant Nos.61006070 and 61076025)
文摘Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrier effect （HCE） has also been proven to be very weak. In this paper, the reason why the annular gate nMOSFETs have good TID but bad HCE resistance is discussed in detail, and an improved design to locate the source contacts only along one side of the annular gate is used to weaken the HCE degradation. The good TID and HCE hardened capability of the design are verified by the experiments for I/O and core nMOSFETs in a 0.18 μm bulk CMOS technology. In addition, the shortcoming of this design is also discussed and the TID and the HCE characteristics of the replacers （the annular source nMOSFETs） are also studied to provide a possible alternative for the designers.
