Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrie...Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrier effect （HCE） has also been proven to be very weak. In this paper, the reason why the annular gate nMOSFETs have good TID but bad HCE resistance is discussed in detail, and an improved design to locate the source contacts only along one side of the annular gate is used to weaken the HCE degradation. The good TID and HCE hardened capability of the design are verified by the experiments for I/O and core nMOSFETs in a 0.18 μm bulk CMOS technology. In addition, the shortcoming of this design is also discussed and the TID and the HCE characteristics of the replacers （the annular source nMOSFETs） are also studied to provide a possible alternative for the designers.展开更多
In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomica...In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N20 plasma passivation is about - 3 × 1011 cm-2.eV-1. With GeO2 passivation, the hysteresis of metal-oxide-semiconductor （MOS） capacitor with A1203 serving as gate dielectric is reduced to - 50 mV, compared with - 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.展开更多
The body current lowering effect of 130 nm partially depleted silicon-on-insulator (PDSOI) input/output (I/O) n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs) induced by total-ionizing dose is obse...The body current lowering effect of 130 nm partially depleted silicon-on-insulator (PDSOI) input/output (I/O) n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs) induced by total-ionizing dose is observed and analyzed. The decay tendency of current ratio of body current and drain current I-b/I-d is also investigated. Theoretical analysis and TCAD simulation results indicate that the physical mechanism of body current lowering effect is the reduction of maximum lateral electric field of the pinch-off region induced by the trapped charges in the buried oxide layer (BOX). The positive charges in the BOX layer can counteract the maximum lateral electric field to some extent.展开更多
Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. ...Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.展开更多
Total ionizing dose effect induced low frequency degradations in 130nm partially depleted silicon-on-insulator （SOI） technology are studied by ^60Co γ -ray irradiation. The experimental results show that the flick...Total ionizing dose effect induced low frequency degradations in 130nm partially depleted silicon-on-insulator （SOI） technology are studied by ^60Co γ -ray irradiation. The experimental results show that the flicker noise at the front gate is not affected by the radiation since the radiation induced trapped charge in the thin gate oxide can be ignored. However, both the Lorenz spectrum noise, which is related to the linear kink effect （LKE） at the front gate, and the flicker noise at the back gate are sensitive to radiation. The radiation induced trapped charge in shallow trench isolation and the buried oxide can deplete the nearby body region and can activate the traps which reside in the depletion region. These traps act as a GR center and accelerate the consumption of the accumulated holes in the floating body. It results in the attenuation of the LKE and the increase of the Lorenz spectrum noise. Simultaneously, the radiation induced trapped charge in the buried oxide can directly lead to an enhanced flicker noise at the back gate. The trapped charge density in the buried oxide is extracted to increase from 2.21×10^18 eV^-1 cm^-3 to 3.59×10^18？eV^-1 cm^-3 after irradiation.展开更多
The bias dependence of radiation-induced narrow-width channel effects（RINCEs） in 65-nm n-type metal-oxidesemiconductor field-effect transistors（NMOSFETs） is investigated. The threshold voltage of the narrow-width6...The bias dependence of radiation-induced narrow-width channel effects（RINCEs） in 65-nm n-type metal-oxidesemiconductor field-effect transistors（NMOSFETs） is investigated. The threshold voltage of the narrow-width65 nm NMOSFET is negatively shifted by total ionizing dose irradiation, due to the RINCE. The experimental results show that the 65 nm narrow-channel NMOSFET has a larger threshold shift when the gate terminal is kept in the ground, which is contrary to the conclusion obtained in the old generation devices. Depending on the three-dimensional simulation, we conclude that electric field distribution alteration caused by shallow trench isolation scaling is responsible for the anomalous RINCE bias dependence in 65 nm technology.展开更多
基金supported by the Key Program of the National Natural Science Foundation of China(Grant No.60836004)the National Natural Science Foundation of China(Grant Nos.61006070 and 61076025)
文摘Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrier effect （HCE） has also been proven to be very weak. In this paper, the reason why the annular gate nMOSFETs have good TID but bad HCE resistance is discussed in detail, and an improved design to locate the source contacts only along one side of the annular gate is used to weaken the HCE degradation. The good TID and HCE hardened capability of the design are verified by the experiments for I/O and core nMOSFETs in a 0.18 μm bulk CMOS technology. In addition, the shortcoming of this design is also discussed and the TID and the HCE characteristics of the replacers （the annular source nMOSFETs） are also studied to provide a possible alternative for the designers.
基金supported by the National Basic Research Program of China(Grant No.2011CBA00601)the National Natural Science Foundation of China(Grant Nos.60625403,60806033,and 60925015)
文摘In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N20 plasma passivation is about - 3 × 1011 cm-2.eV-1. With GeO2 passivation, the hysteresis of metal-oxide-semiconductor （MOS） capacitor with A1203 serving as gate dielectric is reduced to - 50 mV, compared with - 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.
文摘The body current lowering effect of 130 nm partially depleted silicon-on-insulator (PDSOI) input/output (I/O) n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs) induced by total-ionizing dose is observed and analyzed. The decay tendency of current ratio of body current and drain current I-b/I-d is also investigated. Theoretical analysis and TCAD simulation results indicate that the physical mechanism of body current lowering effect is the reduction of maximum lateral electric field of the pinch-off region induced by the trapped charges in the buried oxide layer (BOX). The positive charges in the BOX layer can counteract the maximum lateral electric field to some extent.
基金Supported by the National Science and Technology Major Project of China under Grant No 2011ZX02708-003the National Natural Science Foundation of China under Grant No 61504165the Opening Project of Key Laboratory of Microelectronics Devices and Integrated Technology of Institute of Microelectronics of Chinese Academy of Sciences
文摘Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.
基金Supported by the National Postdoctoral Program for Innovative Talents under Grant No BX201600037the Science and Technology Research Project of Guangdong Province under Grant Nos 20158090901048 and 2015B090912002the Distinguished Young Scientist Program of Guangdong Province under Grant No 2015A030306002
文摘Total ionizing dose effect induced low frequency degradations in 130nm partially depleted silicon-on-insulator （SOI） technology are studied by ^60Co γ -ray irradiation. The experimental results show that the flicker noise at the front gate is not affected by the radiation since the radiation induced trapped charge in the thin gate oxide can be ignored. However, both the Lorenz spectrum noise, which is related to the linear kink effect （LKE） at the front gate, and the flicker noise at the back gate are sensitive to radiation. The radiation induced trapped charge in shallow trench isolation and the buried oxide can deplete the nearby body region and can activate the traps which reside in the depletion region. These traps act as a GR center and accelerate the consumption of the accumulated holes in the floating body. It results in the attenuation of the LKE and the increase of the Lorenz spectrum noise. Simultaneously, the radiation induced trapped charge in the buried oxide can directly lead to an enhanced flicker noise at the back gate. The trapped charge density in the buried oxide is extracted to increase from 2.21×10^18 eV^-1 cm^-3 to 3.59×10^18？eV^-1 cm^-3 after irradiation.
基金Supported by the National Natural Science Foundation of China under Grant Nos 11605282,11505282 and U1532261the West Light Foundation of the Chinese Academy of Sciences under Grant No 2015-XBQN-B-15
文摘The bias dependence of radiation-induced narrow-width channel effects（RINCEs） in 65-nm n-type metal-oxidesemiconductor field-effect transistors（NMOSFETs） is investigated. The threshold voltage of the narrow-width65 nm NMOSFET is negatively shifted by total ionizing dose irradiation, due to the RINCE. The experimental results show that the 65 nm narrow-channel NMOSFET has a larger threshold shift when the gate terminal is kept in the ground, which is contrary to the conclusion obtained in the old generation devices. Depending on the three-dimensional simulation, we conclude that electric field distribution alteration caused by shallow trench isolation scaling is responsible for the anomalous RINCE bias dependence in 65 nm technology.
