Accurate extraction of trap depth responsible for RTS noise in nano-MOSFETs

This paper presents an accurate analytical model of the random telegraph signal （RTS） noise time-constant ratio （-T/-Te） for RTS noise in nano-MOSFETs, in which the Coulomb-blockade effect on trapping and detrapping processes was taken into account. Based on this new model, the depth of the trap responsible for RTS noise in a sample n-type nano-MOSFET is extracted. The results show that large errors will be introduced to the calculated trap depth when the Coulomb-blockade effect is neglected.

Study of Timing Characteristics of NOT Gate Transistor Level Circuit Implemented Using Nano-MOSFET by Analyzing Sub-Band Potential Energy Profile and Current-Voltage Characteristic of Quasi-Ballistic Transport

This paper presents the quasi-ballistic electron transport of a symmetric double-gate (DG) nano-MOSFET with 10 nm gate length and implementation of logical NOT transistor circuit using this nano-MOSFET. Theoretical calculation and simulation using NanoMOS have been done to obtain parameters such as ballistic efficiency, backscattering mean free path, backscattering coefficient, critical length, thermal velocity, capacitances, resistance and drain current. NanoMOS is an on-line device simulator. Theoretical and simulated drain current per micro of width is closely matched. Transistor loaded NOT gate is simulated using WinSpice. Theoretical and simulated value of rise time, fall time, propagation delay and maximum signal frequency of logical NOT transistor level circuit is closely matched. Quasi-ballistic transport has been investigated in this paper since modern MOSFET devices operate between the drift-diffusion and ballistic regimes. This paper aims to enable modern semiconductor device engineers to become familiar with both approaches.

Modeling of current mismatch induced by random dopant fluctuation in nano-MOSFETs

Deviation of threshold voltage and effective mobility due to random dopant fluctuation is proposed.An improved 65 nm average drain current MOS model calledαlaw is utilized after fitting HSPICE simulating data and extracting process parameters.Then,a current mismatch model of nanoscale MOSFETs induced by random dopant fluctuation is presented based on propagation of variation theory.In test conditions,the calculated standard deviation applying this model,compared to 100 times Monte-Carlo simulation data with HSPICE,indicates that the average relative error and relative standard deviation is 0.24%and 0.22%,respectively.The results show that this mismatch model is effective to illustrate the physical mechanism,as well as being simple and accurate.

纳米银双面烧结SiC半桥模块封装技术

为满足雷达阵面高功率密度的需求,SiC宽禁带半导体器件在电源模块应用中逐步取代传统硅功率器件。传统焊接及导电胶粘工艺存在导电性能差、热阻大、高温蠕变等缺点,无法发挥SiC功率器件高结温和高功率的优势。纳米银烧结是大功率器件最合适的界面互连技术之一,具有低温烧结高温使用的优点和良好的高温工作特性。文中针对高功率电源模块大电流传输对低压降及高效散热的需求,基于高功率半桥电源模块开展了SiC芯片的纳米银双面烧结工艺技术研究,突破了成型银焊片制备、纳米银焊膏高平整度点涂、无压烧结等关键技术,并通过烧结界面微观分析以及芯片剪切强度和焊片剥离强度测试对烧结工艺参数进行了优化。最后对半桥模块进行了静态测试和双脉冲测试。该模块的栅极泄漏电流<1.5 n A,开关切换时间<125 ns,漏极电压过冲<12.5%,满足产品应用需求。

纳米MOSFET器件电流噪声测试方法研究

针对常规纳米尺度电子元器件的噪声特性,研究其噪声的基本测试条件,并建立测试系统。在屏蔽条件下采用低温装置和超低噪声前置放大器,能有效抑制外界干扰。应用该系统对实际纳米MOSFET器件进行噪声测试得到其电流噪声,在测试基础上通过计算分别得到热噪声和散粒噪声,同时分析器件工作在亚阈区和反型区下的电流噪声随源漏电压和电流的变化关系。结果表明测试结果与理论分析吻合,验证了测试系统的准确性。

纳米级MOSFET多晶区量子修正解析模型

利用ISE8.0的DESSIS,对多晶区量子力学效应进行了摸拟。结果表明,纳米级MOSFET多晶区内的量子效应不可忽略,且它对器件特性的影响与多晶耗尽效应相反。从密度梯度模型,简化得到多晶区量子效应修正,并建立了多晶区内量子效应的集约模型。该模型与数值模拟结果吻合。

研究纳米尺寸MOSFETs亚阈值特性的一种新方法(英文)

提出了一种用于研究纳米尺寸MOSFETs亚阈值特性的新方法——摄动法.使用摄动法来求解泊松方程,使得在纳米尺寸MOSFETs工作中不再起作用的耗尽层近似和页面电荷模型在求解过程中被避免,由此可以解得一个指数形式的亚阈值电流的表达式,从而得到关于亚阈值摆幅变化的解析表达式.通过把所建立的解析模型的计算结果和Medici仿真软件的模拟结果进行比较,可以证明该适用于分析亚阈值区工作特性的模型具有相当的准确性和可用性.

摄动法研究纳米MOSFETs亚阈值特性

采用了一种新的方法研究纳米金属-氧化物-半导体场效应管(MOSFETs)的亚阈值特性,即正则摄动法.由于在纳米MOSFETs中,常用的耗尽近似和页面电荷模型(charge-sheetmodel)不再适用,导致泊松方程由线性变成非线性形式.利用正则摄动法求解非线性泊松方程可以得到纳米MOSFETs亚阈值电流和亚阈值摆幅指数依赖外加偏压的解析表达式.通过与二维器件模拟软件MEDICI模拟结果比较,证明了该方法及结果的有效性.

纳米级MOSFET器件模拟的载流子输运模型

随着半导体微细加工技术的发展,预计硅SOC的集成度可达万亿个晶体管,单个晶体管的尺寸将达到10nm范围内。因此从理论上研究纳米尺寸器件的性能和特性对发展超大规模集成电路尤为重要。综述了纳米级MOSFET器件数值模拟的量子模型,以及在该模型下用到的几种载流子输运模型,并结合模拟结果对这一模型作了评价。

新一代纳米级器件物理特性仿真工具——SenTaurus Device

介绍了Synopsys Inc.新近推出的新一代纳米层次器件物理特性仿真工具——SenTaurus Device的功能特点以及进行器件物理特性仿真的典型流程。重点介绍了为实现nm级器件物理特性的模拟引入的诸多近代器件物理模型。利用SenTaurus Device对基于Sentaurus Process生成的一个90nm NMOS器件进行了器件物理特性仿真,并给出了相应结果。

基于TCAD软件的纳米MOS器件特性分析

该文借助计算机仿真软件以32nmNMOS器件为例，研究了短沟道器件的特性。通过采用迁移率、碰撞离化、载流子复合等物理模型在模拟软件中建立了合适的器件模型。在此基础上对比分析了0．18m长沟与32nm短沟NMOS器件的输入、输出以及击穿特性。此外，讨论了不同栅氧厚度对纳米器件输入特性和击穿特性的影响。较薄的栅氧设计能显著降低器件的功耗，提升集成电路与系统的性能，同时对可靠性造成一定影响。

Physical Parameter Variation Analysis on the Performance Characteristics of Nano DG-MOSFETs

DG-MOSFETs are the most widely explored device architectures for nano-scale CMOS circuit design in sub-50 nm due to the improved subthreshold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film (tsi < 10 nm) DG-MOS structures, charge carriers are affected by tsi- induced quantum confinement along with the confinement caused by a very high electric field at the interface. Therefore, quantum confinement effects on the device characteristics are also quite important and it needs to be incorporated along with short channel effects for nano-scale circuit design. In this paper, we analyzed a DG-MOSFET structure at the 20 nm technology node incorporating quantum confinement effects and various short channel effects. The effect of physical parameter variations on performance characteristics of the device such as threshold voltage, subthreshold slope, ION - IOFF ratio, DIBL, etc. has been investigated and plotted through extensive TCAD simulations. The physical parameters considered in this paper are operating temperature (Top), channel doping concentration (Nc), gate oxide thickness (tox) and Silicon film thickness (tsi). It was observed that quantum confinement of charge carriers significantly affected the performance characteristics (mostly the subthreshold characteristics) of the device and therefore, it cannot be ignored in the subthreshold region-based circuit design like in many previous research works. The ATLASTM device simulator has been used in this paper to perform simulation and parameter extraction. The TCAD analysis presented in the manuscript can be incorporated for device modeling and device matching. It can be used to illustrate exact device behavior and for proper device control.

准弹道输运纳米MOSFET散粒噪声的抑制研究

目前研究准弹道输运纳米MOSFET散粒噪声的抑制时,采取了完全不考虑其抑制,或只强调抑制的存在而并未给出抑制公式的方式进行研究.本文基于Navid模型推导了准弹道输运纳米MOSEET散粒噪声,并得到了其在费米作用、库仑作用和二者共同作用三种情形下的抑制因子.在此基础上,对各抑制因子随源漏电压、栅极电压、温度及源漏掺杂浓度的变化特性进行了研究.两者共同作用的抑制因子随源漏电压和栅极电压变化特性与文献中给出的实验结论相符合,从而对实验上得到两者共同作用下的抑制因子随源漏电压和栅极电压的变化特性给出了理论解释.

基于Monte Carlo模拟的实际纳米MOSFET散粒噪声抑制研究

实验测量和理论结果均表明,随着MOS器件尺寸缩小到纳米尺度,其过剩噪声的主要成分将从以热噪声为主转变为以散粒噪声为主,且散粒噪声受费米抑制作用和库仑抑制作用.而目前对纳米MOSFET散粒噪声抑制的研究时,采取了完全不考虑其抑制,或者只是强调抑制的存在而并未给出具体的抑制分析.本文将采用蒙特卡罗(Monte Carlo)模拟方法对实际纳米MOSFET电流噪声进行数值模拟研究,并考虑费米作用和库仑作用对散粒噪声的抑制影响,分别得到费米抑制因子和费米与库仑共同作用时的抑制因子.在此基础上,重点考察栅极电压、源漏电压、温度和掺杂浓度对散粒噪声抑制的影响及其关系的理论分析,得到的模拟结果与文献给出的实验结果和介观理论结果相吻合.

实际纳米MOSFET电流噪声及其相关特性分析

实际纳米MOSFET电流噪声为散粒噪声和热噪声,且散粒噪声受到费米作用和库仑作用的抑制.而现有文献研究实际纳米MOSFET电流噪声时,采取了完全不考虑其散粒噪声的抑制,或者只是强调抑制的存在而并未给出具体的抑制分析.本文基于Navid模型推导了实际纳米MOSFET电流噪声,并考虑费米作用和库仑作用对散粒噪声的抑制.在此基础上,对电流噪声随沟道长度、温度、源漏电压和栅极电压的变化特性进行了分析,其变化规律与文献中已有的实验和理论变化相一致.沟道长度越短,温度越低,源漏电压越大和栅极电压越低,电流噪声主要以散粒噪声为主.

基于纳米MOSFET噪声的背散射系数研究

传统噪声理论提取背散射系数时,引入的参量较多并依赖量子力学计算,或是采取大量的假设而使得到的结论存在偏差.本文将基于Navid模型推导MOSFET噪声的背散射系数,进一步得到了短沟道器件在线性区和饱和区的背散射系数,并给出测量背散射系数的方法.在此基础上,对背散射系数随沟道长度、偏置电压和温度的变化特性进行分析,除此之外,用实验和Monte Carlo模拟验证了背散射系数与偏置电压特性,该方法得到的背散射系数与各参量的变化特性与文献给出的结果相吻合.

纳米MOSFET迁移率解析模型

从玻尔兹曼方程出发,重新计算了纳米MOSFET沟道内的载流子所服从的分布函数,特别是考虑了纳米MOSFET横向电场和纵向电场之间的相互作用,并且以得到的非平衡状态下的分布函数为基础,考虑载流子寿命和速度的统计分布,给出了纳米MOSFET载流子迁移率的解析表达式.通过与数值模拟结果进行比较和分析,该迁移率解析模型形式简洁、物理概念清晰,且具有相当精度.