A PRIORITY-BASED POLLING SCHEDULING ALGORITHM FOR ARBITRATION POLICY IN NETWORK ON CHIP

A solution is imperatively expected to meet the efficient contention resolution schemes for managing simultaneous access requests to the communication resources on the Network on Chip (NoC). Based on the ideas of conflict-free transmission, priority-based service, and dynamic self-adaptation to loading, this paper presents a novel scheduling algorithm for Medium Access Control (MAC) in NoC with the researches of the communication structure features of 2D mesh. The algorithm gives priority to guarantee the Quality of Service (QoS) for local input port as well as dynamic adjustment of the performance of the other ports along with input load change. The theoretical model of this algorithm is established with Markov chain and probability generating function. Mathematical analysis is made on the mean queue length and the mean inquiry cyclic time of the system. Simulated experiments are conducted to test the accuracy of the model. It turns out that the findings from theoretical analysis correspond well with those from simulated experiments. Further more, the analytical findings of the system performance demonstrate that the algorithm enables effectively strengthen the fairness and stability of data transmissions in NoC.

An Evaluation of Routing Algorithms in Traffic Engineering and Quality of Service Provision of Network on Chips

Nowadays the number of cores that are integrated into NoC (Network on Chip) systems is steadily increasing, and real application traffic, running in such multi-core environments requires more and more bandwidth. In that sense, NoC architectures should be properly designed so as to provide efficient traffic engineering, as well as QoS support. Routing algorithm choice in conjunction with other parameters, such as network size and topology, traffic features (time and spatial distribution), as well as packet injection rate, packet size, and buffering capability, are all equivalently critical for designing a robust NoC architecture, on the grounds of traffic engineering and QoS provision. In this paper, a thorough numerical investigation is achieved by taking into consideration the criticality of selecting the proper routing algorithm, in conjunction with all the other aforementioned parameters. This is done via implementation of four routing evaluation traffic scenarios varying each parameter either individually, or as a set, thus exhausting all possible combinations, and making compact decisions on proper routing algorithm selection in NoC architectures. It has been shown that the simplicity of a deterministic routing algorithm such as XY, seems to be a reasonable choice, not only for random traffic patterns but also for non-uniform distributed traffic patterns, in terms of delay and throughput for 2D mesh NoC systems.

Design of Efficient Router with Low Power and Low Latency for Network on Chip

The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.

A fuzzy integrated congestion-aware routing algorithm for network on chip

Network on chip(NoC)is an infrastructure providing a communication platform to multiprocessor chips.Furthermore,the wormhole-switching method,which shares resources,was used to increase its efficiency;however,this can lead to congestion.Moreover,dealing with this congestion consumes more energy and correspondingly leads to increase in power consumption.Furthermore,consuming more power results in more heat and increases thermal fluctuations that lessen the life span of the infrastructures and,more importantly,the network’s performance.Given these complications,providing a method that controls congestion is a significant design challenge.In this paper,a fuzzy logic congestion control routing algorithm is presented to enhance the NoC’s performance when facing congestion.To avoid congestion,the proposed algorithm employs the occupied input buffer and the total occupied buffers of the neighboring nodes along with the maximum possible path diversity with minimal path length from instant neighbors to the destination as the selection parameters.To enhance the path selection function,the uncertainty of the fuzzy logic algorithm is used.As a result,the average delay,power consumption,and maximum delay are reduced by 14.88%,7.98%,and 19.39%,respectively.Additionally,the proposed method enhances the throughput and the total number of packets received by 14.9%and 11.59%,respectively.To show the significance,the proposed algorithm is examined using transpose traffic patterns,and the average delay is improved by 15.3%.The average delay is reduced by 3.8%in TMPEG-4(treble MPEG-4),36.6%in QPIP(quadruplicate PIP),and 20.9%in TVOPD(treble VOPD).

MSONoC: a non-blocking optical interconnection network for inter cluster communication

Electric router is widely used for multi-core system to interconnect each other. However, with the increasing number of processor cores, the probability of communication conflict between processor cores increases, and the data delay increases dramatically. With the advent of optical router, the traditional electrical interconnection mode has changed to optical interconnection mode. In the packet switched optical interconnection network, the data communication mechanism consists of 3 processes: link establishment, data transmission and link termination, but the circuit-switched data transmission method greatly limits the utilization of resources. The number of micro-ring resonators in the on-chip large-scale optical interconnect network is an important parameter affecting the insertion loss. The proposed λ-route, GWOR, Crossbar structure has a large overall network insertion loss due to the use of many micro-ring resonators. How to use the least micro-ring resonator to realize non-blocking communication between multiple cores has been a research hotspot. In order to improve bandwidth and reduce access latency, an optical interconnection structure called multilevel switching optical network on chip(MSONoC) is proposed in this paper. The broadband micro-ring resonators(BMRs) are employed to reduce the number of micro-ring resonators(MRs) in the network, and the structure can provide the service of non-blocking point to point communication with the wavelength division multiplexing(WDM) technology. The results show that compared to λ-route, GWOR, Crossbar and the new topology structure, the number of micro-ring resonators of MSONoC are reduced by 95.5%, 95.5%, 87.5%, and 60% respectively. The insertion loss of the minimum link of new topology, mesh and MSONoC structure is 0.73 dB, 0.725 dB and 0.38 dB.

PERFORMANCE ANALYSIS OF MINIMAL PATH FAULT TOLERANT ROUTING IN NOC

Occurrence of faults in Network on Chip(NoC) is inevitable as the feature size is con-tinuously decreasing and processing elements are increasing in numbers.Faults can be revocable if it is transient.Transient fault may occur inside router,or in the core or in communication wires.Examples of transient faults are overflow of buffers in router,clock skew,cross talk,etc..Revocation of transient faults can be done by retransmission of faulty packets using oblivious or adaptive routing algorithms.Irrevocable faults causes non-functionality of segment and mainly occurs during fabrication process.NoC reliability increases with the efficient routing algorithms,which can handle the maximum faults without deadlock in network.As transient faults are temporary and can be easily revoked using re-transmission of packet,permanent faults require efficient routing to route the packet by bypassing the nonfunctional segments.Thus,our focus is on the analysis of adaptive minimal path fault tolerant routing to handle the permanent faults.Comparative analysis between partial adaptive fault tolerance routing West-First,North-Last,Negative-First,Odd Even,and Minimal path Fault Tolerant routing(MinFT) algorithms with the nodes and links failure is performed using NoC Interconnect RoutinG and Application Modeling simulator(NIRGAM) for the 2D Mesh topology.Result suggests that MinFT ensures data transmission under worst conditions as compared to other adaptive routing algorithms.

单片机实验系统中网络串口的使用

以单片机实验系统中网络串口的使用为例,介绍了单片机网络串口实现网络数据传输的方法.

数字矿山通信网络无线基站的设计与实现

针对现有矿井通信系统各自封闭、相互之间不能兼容的现状,提出基于WiFi的数字矿山通信网络系统的设计方案,设计开发用于构建通信网络系统的无线基站。该无线基站采用先进的可编程片上系统技术,实现WiFi语音通话、WiFi视频监视、人员定位等多种功能,为矿山资源开采的可视化、可知化和生产过程的可控化提供技术支持。测试结果表明,该基站网络性能好,能满足实际应用的要求。

基于单边通信协议的片上网络传输接口设计

为了提升处理单元与片上网络之间的数据交互能力,基于单边通信协议设计了一款片上网络传输接口。该接口通过直接存储访问实现了存储器与网络接口间的高效数据搬移,降低了数据包的发送和接收延时,同时减少了CPU的干预。16核片上多处理器环境下的实验结果表明,对比CPU干预型的片上网络传输接口,论文设计的网络接口能有效提升片上多核处理器的并行计算性能。

电力负荷无线分层控制系统

本文介绍了一种采用微机及单片机组同,进行分层控制的电力负荷无线控制系统,详述了其工作原理、硬件结构及功能设计。