基于流水线计算的3D NoC测试规划研究

为了提高三维片上网络(3D NoC)资源内核的测试效率,提出一种在功耗约束条件下多播流水线并行测试同构核与单播测试异构核相结合的方法对IP核进行测试。为了减少测试数据因资源冲突而进行等待的时间,设计一种改进XYZ路由算法,并采用改进人工蜂群(ABC)算法求解最佳测试规划方案。以国际标准电路测试集ITC'02作为实验对象,结果表明,测试时间最大优化率达到15.45%,与其他测试规划方法相比该文方法能有效地提高并行测试效率。

用于MIMO检测的基于NoC的多核动态可重构架构

随着无线通信技术的发展,实现多输入多输出(MIMO)系统检测性能与复杂度之间的最优权衡日益困难,深度学习DL为此提供了新方向。文中提出基于片上网络(NoC)的多核动态可重构架构MCDBP,以提高基于DL的MIMO检测算法的性能,并增强架构的可编程性和扩展性。MCDBP通过集成轻量级计算内核及片上网络互连,并行处理矢量-矩阵乘法、常数-矢量乘法、矢量点积、矢量加法等大多数深度展开网络的基本运算,有效提高复杂MIMO检测性能。架构的创新在于可重构的处理元件PE设计,可以依据DL驱动的MIMO检测需求动态调整。该设计对基于DL的MIMO检测算法共性进行深入分析,支持多种基本运算模式,展现极高灵活性。实验结果显示,MCDBP在执行基于DL的MIMO检测算法时,与通用CPU相比,可以实现12.66~22.98的加速比,算法性能有所提高,可以适应不同应用场景。

Groundwater Level Prediction Using Artificial Neural Networks: A Case Study in Tra Noc Industrial Zone, Can Tho City, Vietnam

The objective of this study is to predict groundwater levels (GWLs) under different impact factors using Artificial Neural Network (ANN) for a case study in Tra Noc Industrial Zone, Can Tho City, Vietnam. This can be achieved by evaluating the current state of groundwater resources (GWR) exploitation, use and dynamics;setting-up, calibrating and validating the ANN;and then predicting GWLs at different lead times. The results show that GWLs in the study area have been found to reduce rapidly from 2000 to 2015, especially in the Middle-upper Pleistocene (qp2-3) and upper Pleistocene (qp3) due to the over-withdrawals from the enterprises for production purposes. Concerning this problem, an Official Letter of the People’s Committee of Can Tho City was issued and taken into enforcement in 2012 resulting in the reduction of exploitation. The calibrated ANN structures have successfully demonstrated that the GWLs can be predicted considering different impact factors. The predicted results will help to raise awareness and to draw an attention of the local/central government for a clear GWR management policy for the Mekong delta, especially the industrial zones in the urban areas such as Can Tho city.

Design of an unbuffered switch for network on-chip

In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.

MSONoC: a non-blocking optical interconnection network for inter cluster communication

Electric router is widely used for multi-core system to interconnect each other. However, with the increasing number of processor cores, the probability of communication conflict between processor cores increases, and the data delay increases dramatically. With the advent of optical router, the traditional electrical interconnection mode has changed to optical interconnection mode. In the packet switched optical interconnection network, the data communication mechanism consists of 3 processes: link establishment, data transmission and link termination, but the circuit-switched data transmission method greatly limits the utilization of resources. The number of micro-ring resonators in the on-chip large-scale optical interconnect network is an important parameter affecting the insertion loss. The proposed λ-route, GWOR, Crossbar structure has a large overall network insertion loss due to the use of many micro-ring resonators. How to use the least micro-ring resonator to realize non-blocking communication between multiple cores has been a research hotspot. In order to improve bandwidth and reduce access latency, an optical interconnection structure called multilevel switching optical network on chip(MSONoC) is proposed in this paper. The broadband micro-ring resonators(BMRs) are employed to reduce the number of micro-ring resonators(MRs) in the network, and the structure can provide the service of non-blocking point to point communication with the wavelength division multiplexing(WDM) technology. The results show that compared to λ-route, GWOR, Crossbar and the new topology structure, the number of micro-ring resonators of MSONoC are reduced by 95.5%, 95.5%, 87.5%, and 60% respectively. The insertion loss of the minimum link of new topology, mesh and MSONoC structure is 0.73 dB, 0.725 dB and 0.38 dB.

Designing cost-effective network-on-chip by dual-channel access mechanism

A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol （IP） has only one chan- nel to access the on-chip network. When the network is relatively idle, the injection rate is too small to make good use of the network resource. When the network is relatively busy, the ejection rate is so small that the packets in the network cannot leave immediately, and thus the probability of congestion is increased. In the dual-channel access mechanism, the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface （NI） and local port of routers. Therefore, the communication performance is improved. Experimental results show that compared with traditional single-channel access mechanism, the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase.

Twist-Routing Algorithm for Faulty Network-on-Chips

This paper introduces Twist-routing, a new routing algorithm for faulty on-chip networks, which improves Maze-routing, a face-routing based algorithm which uses deflections in routing, and archives full fault coverage and fast packet delivery. To build Twist-routing algorithm, we use bounding circles, which borrows the idea from GOAFR+ routing algorithm for ad-hoc wireless networks. Unlike Maze-routing, whose path length is unbounded even when the optimal path length is fixed, in Twist-routing, the path length is bounded by the cube of the optimal path length. Our evaluations show that Twist-routing algorithm delivers packets up to 35% faster than Maze-routing with a uniform traffic and Erdos-Rényi failure model, when the failure rate and the injection rate vary.

面向能耗和延时的NoC映射方法

随着对NoC平台研究的逐步深入，如何将规模庞大的应用合理地映射到NoC半台上成为亟待解决的问题之一．本文基于二维网格结构NoC平台，建立了旨在优化系统通信能耗和执行时间的统一目标函数．提出了通过优化链路负载分布间接优化延时的方法，避免了NoC等待延时精确建模的难题．并且采用蚁群算法实现了面向能耗和延时的NoC映射．调整参数λ，可以选择单一目标或者联合目标优化．本文还对映射结果进行了执行时间模拟．实验结果显示：与随机映射相比，单一目标优化在通信能耗和执行时间上分别能节省（30％～47％）和（20％～39％），而联合目标优化则能在能量支配的映射方案中进一步挖掘时间维度的潜力．

基于2D Mesh的NoC路由算法设计与仿真

在研究Turn Model模型的基础上,提出一种基于2D Mesh结构的XY-YX路由算法,是一种确定性的无死锁的最短路径路由算法。给出无死锁的证明,通过片上网络(NoC)模拟仿真实验平台NIRGAM,将该算法在一个4×4的2D Mesh网络中进行仿真。

NoC:下一代集成电路主流设计技术

从SoC的定义出发,依据“PC参考系准则”、“十年变革规律”、“半导体技术发展规律”等基本规律,提出并论证了“NoC是下一代集成电路主流设计技术”的观点,概括了NoC基础理论体系的主要研究领域;简要分析了集成电路NoC体系结构领域可能的关键技术。NoC技术从体系结构上彻底解决了SoC的总线结构所固有的三大问题:由于地址空间有限而引起的扩展性问题,由于分时通讯而引起的通讯效率问题,以及由于全局同步而引起的功耗和面积问题。

处理器可靠性约束的电压频率岛NoC能耗优化

该文针对支持电压频率岛的NoC能耗优化问题,提出了基于电压频率岛划分、分配以及任务映射的能耗优化方法。该方法通过基于处理器可靠性约束的电压频率岛划分,降低了处理器能耗;利用近凸区域选择的电压频率岛分配策略,减少了不同电压岛间复杂路由器的个数;借助量子粒子群算法优化了NoC映射,降低了系统的通信能耗。实验结果表明,该文算法在满足NoC处理器可靠性要求的前提下,可显著降低NoC系统能耗。

基于内建自测技术的Mesh结构NoC无虚通道容错路由算法

在Zhang's算法绕行思想的基础上,提出了一种2D-Mesh结构片上网络无虚通道容错路由算法,用于解决多故障节点情况下片上网络的无虚通道容错路由问题.算法利用内建自测试机制获取故障区域的位置信息,通过优化绕行策略来均衡故障区域周围链路的负载并减少部分数据的绕行距离.针对8×8的2D-Mesh网络的仿真表明,与Chen's算法相比,在故障区域大小为2×2,网络时延为70 cycles的情况下,随着故障区域位置的变化所提算法可提高1.2%到4.8%的网络注入率.且随着故障区域面积的扩大,所提算法在减少通信时延,提高网络吞吐量方面的作用更为明显.

面向通信能耗的3D NoC映射研究

对于传统的平面结构,三维片上网络(3D NoC)具有更好的集成度和性能,在单芯片内部可以集成更多的处理器核。3D NoC作为2D NoC的结构拓展,在性能提高和低功耗设计方面更具优越性,成为多核系统芯片结构的主流架构。映射就是应用某种算法寻找一种最优方案,将通信任务图的子任务分配到NoC的资源节点上,保证NoC的通信能耗最小。参照2D NoC的研究方法,提出了针对3D网格NoC的通信能耗模型,采用蚁群算法实现了面向通信能耗的NoC映射。实验结果表明,面向不同网络规模的3D网格NoC平台,蚁群映射同随机映射相比,通信能耗降低可以达23%～42%。

功耗限制下的NoC测试端口的优化选择方法

提出了一种NoC测试端口位置和数量的优化选取的方法,它在系统功耗限制的条件下,确定input/output端口的对数,以所有核测试路径总和最短为目标,优化选取NoC测试端口的最佳位置。本方案在测试功耗不超过系统允许的最大功耗条件下,最大限度地选取测试端口的对数来进行并行测试,从而能高效地完成对核的测试,同时又能有效地避免因测试带来的器件损坏。实验结果表明这种方法提高了测试效率,降低了NoC的总体测试代价。

片上通信结构——共享总线和NoC的分析与比较

采用模块化方法对集中式仲裁共享总线和二维网格片上网络(Network on Chip,NoC)的硬件开销和延迟进行了数学上的分析。在此基础上,通过可综合Verilog代码对这两种片上通信结构在RTL级进行描述,并建立了这两种通信方式的周期准确级的功能验证和性能分析环境。结果表明,在同样工艺条件下,共享总线的面积与NoC相比相当小;但对于大规模片上系统通信,NoC的吞吐效率及带宽明显优于共享总线。

针对瞬时故障和间歇性故障的NoC链路容错方法

片上网络中链路是路由器之间连接的关键通路,其发生故障将严重影响网络性能.针对这一问题,提出了一种针对瞬时和间歇性故障的高可靠链路容错方法,该方法可以在网络中实时检测数据是否发生错误,并以此定义瞬时故障和间歇性故障,从而进行容错.在减轻网络拥塞和延时的同时,保证了数据的正确传输,有效保障了系统的高可靠性.当链路中发生瞬时故障导致数据出错且不能正确纠正时,通过设置的重传缓冲区内备份的数据重新进行传输.当链路中发生间歇性故障导致数据出错且不能正确纠正时,数据包传输被截断,对被截断的数据重新添加头微片或尾微片,从而进行重新路由或资源释放.实验结果表明:该容错方法在不同故障情况下较对比对象,均较大地降低了延时,提高了吞吐率,该方法能有效地提高网络的可靠性,保证了系统性能.

功耗优先的NoC通讯架构测试方法

文章提出了一种针对片上网络通讯架构的测试方法,该测试方法可以测试路由器各端口以及各条链路;其主要目标是优先考虑降低测试NoC通讯架构过程中所产生的功耗,还可避免局部热点的产生。文中方法根据片上网络中各通讯节点的不同位置,合理地安排测试数据包的转发方式,以减少测试过程中复制转发数据包的数量,从而达到降低测试功耗的目的。实验结果表明,这种方法在提高测试效率的基础上,有效地降低了NoC的测试功耗。

基于拥塞预测的NoC自适应仲裁方法

传统用于总线系统或互联网的仲裁方法已不能很好地适应NoC应用环境。围绕NoC系统性能的关键影响因素——拥塞状态,提出了一种基于全局和本地拥塞预测的仲裁策略(GLCA),以改善NoC网络延迟。实验结果表明,相对于RR方法,新仲裁算法使得网络平均包延迟和平均吞吐量最大分别可改善20.5%和8%,并且在不同负载条件下都保持了其优势。综合结果显示,GLCA与RR方法相比,路由器仅在组合逻辑上有少许增加(25.7%)。

基于故障链路缓存再利用的NoC容错路由算法

建立故障模型是进行片上网络容错研究的基础,传统的细粒度故障模型未能有效地区分链路故障和通道故障.为了进一步提高片上资源的利用率,构建了一种粒度更细的微粒度故障模型,并在该模型的基础上提出了基于故障链路缓存再利用的容错路由算法.该算法为每个通信节点增加4条自收发通道,并采用基于缓存再利用的透传机制,通过复用故障链路两端的正常缓存和通道来透传故障通道上的数据包,提高了数据包采用最优输出端口的概率.实验结果表明,文中算法在高故障比例的片上网络中优势明显,且能以相对较小的硬件开销换取平均吞吐量、平均延迟和数据包平均跳数等性能的大幅度提升.

二维网格NoC中资源-网络接口设计与实现

通常把使用片上网络通讯的多核SoC称为NoC,各类资源(处理器、存储器等)与片上网络之间的接口称为资源-网络接口。文章基于二维网格的通讯方式,设计了其间的资源-网络接口,讨论了基于FPGA的实现技术。使用具体应用实例——轨迹显示方案,对设计进行验证。实验表明,在60 MHz的频率下,使用该接口的NoC系统原型能够稳定工作。