Analytical Modeling of a Multi-queue Nodes Network Router

This paper presents the derivation of an analytical model for a multi-queue nodes network router, which is referred to as the multi-queue nodes （mQN） model. In this model, expressions are derived to calculate two performance metrics, namely, the queue node and system utilization factors. In order to demonstrate the flexibility and effectiveness of the mQN model in analyzing the performance of an mQN network router, two scenarios are performed. These scenarios investigated the variation of queue nodes and system utilization factors against queue nodes dropping probability for various system sizes and packets arrival routing probabilities. The performed scenarios demonstrated that the mQN analytical model is more flexible and effective when compared with experimental tests and computer simulations in assessing the performance of an mQN network router.

Designs of 3D Mesh and Torus Optical Network-on-Chips:Topology,Optical Router and Routing Module

As a nanometer-level interconnection,the Optical Network-on-Chip(ONoC)was proposed since it was typically characterized by low latency,high bandwidth and power efficiency. Compared with a 2-Dimensional(2D)design,the 3D integration has the higher packing density and the shorter wire length. Therefore,the 3D ONoC will have the great potential in the future. In this paper,we first discuss the existing ONoC researches,and then design mesh and torus ONoCs from the perspectives of topology,router,and routing module,with the help of 3D integration. A simulation platform is established by using OPNET to compare the performance of 2D and 3D ONoCs in terms of average delay and packet loss rate. The performance comparison between 3D mesh and 3D torus ONoCs is also conducted. The simulation results demonstrate that 3D integration has the advantage of reducing average delay and packet loss rate,and 3D torus ONoC has the better performance compared with 3D mesh solution. Finally,we summarize some future challenges with possible solutions,including microcosmic routing inside optical routers and highly-efficient traffic grooming.

Neural Network Based Scheduling for Variable-Length Packets in Gigabit Router with Crossbar Switch Fabric and Input Queuing

A high-speed and effective packet scheduling method is crucial to the performance of Gigabit routers. The paper studies the variable-length packet scheduling problem in Gigabit router with crossbar switch fabric and input queuing, and a scheduling method based on neural network is proposed. For the proposed method, a scheduling system structure fit for the variable-length packet case is presented first, then some rules for scheduling are given. At last, an optimal scheduling method using Hopfield neural network is proposed based on the rules. Furthermore, the paper discusses that the proposed method can be realized by hardware circuit. The simulation result shows the effectiveness of the proposed method.

Powering Next-Generation Broadband Networks: ZTE's World-First Flexible, Configurable Router

16 September 2013, Shenzhen--ZTE today unveiled the world＇s first flexible, reconfigurable terabit router that allows customers to build the highest-performance broadband networks. The terabit router supports the deployment of multiple line cards with processing capabilities of 10 Gbps to 1 Tbps. It also supports the deployment of modules that can scale throughput from 200 Gbps to 18 Tbps. For easy installation in a range of environments, the router interfaces are flexible and the component design is loose-coupled. This allows customers to customize networks to their needs and promotes adaptability, consistency, and continuity.

Route Optimization for Network Mobility Based Aeronautical Network Using Correspondent Router

The future aeronautical network will be based on IPv6 and the services over the aeronautical network will be classified into 3 domains: Air Traffic Services (ATS), Airline Operational Services (AOS) and Passenger Information and Entertainment Services (PIES), among which the ATS and AOS domains are important for aircraft safety and airline business operation. Some schemes have been proposed to provide IP mobility support for aeronautical network, and Network Mobility (NEMO) scheme is the most promising one. However, using NEMO technology will lead to sub-optimal routing, so route optimization technology is highly desired for NEMO. A route optimization scheme is proposed for the ATS and AOS domains, which introduces the Correspondent Routers to realize the optimal routing and employs an improved procedure to reduce the handoff delay. The route optimization for the PIES domain is also discussed to provide better performance for some special scenarios.

Design of Efficient Router with Low Power and Low Latency for Network on Chip

The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.

Two-stage Planning Method for Energy Router Considering Its Optimal Operation in Distribution Networks

An energy router can effectively optimize the network loss and power quality of distribution networks. The optimal configuration of the energy router is relatively complex because issues dynamically influence each other, such as the location of the energy router, optimal number and capacity of its ports, and building new distribution lines for the ports. Presently, there has been very few research studies on the practical problems for the energy router. In this paper, a planning model of an energy router combined with the distribution network is established, which fully exploits the active and reactive power control abilities of the energy router to optimize the operation of the grid. The configuration problem is decoupled into two stages. The upper layer determines the location of the energy router and the parameters of the candidate new distribution lines for the ports. The lower layer calculates the optimal configuration of the energy router by minimizing the total annual cost. Because of the same rated bus voltage in the distribution network, the existing structure of the energy router is changed to be more applicable for the distribution network, and then the power flow model of the energy router is also modified. Due to the nonlinearity of the model, the planning model is converted into a mixed-integer second-order cone model to solve efficiently. In addition, some core factors influencing the optimal scheme of the energy router are also analyzed in this paper. Simulation results show that the optimal scheme of the energy router can significantly improve the economic deployment of the energy router, and optimize the network loss and power quality of the distribution network.

Planning Model for Energy Routers Considering Peer-to-Peer Energy Transactions Among Multiple Distribution Networks

A high proportion of renewable energy affects the power quality of distribution networks,and surplus energy will be sold to the upstream grid at a low price.In this paper,considering peer-to-peer energy transactions,the energy router-based multiple distribution networks are analyzed to solve the above problems and realize collaborative consumption of renewable energy.Presently,the investing cost of an energy router is high,and research on the economic operation of energy routers in distribution networks is little.Therefore,this paper establishes a planning model for energy routers considering peer-to-peer energy transactions among distribution networks,and explores the benefits of peer-to-peer energy transactions through energy router based multiple distribution networks.A structure of an energy router suitable for peer-to-peer energy transactions is selected,and a power flow calculation model based on a multilayer structure is established.The energy router’s scheduling model is established,and unique functions of the energy router and revenue of each distribution network are considered.A power flow calculation model based on peer-to-peer interconnection of multiple distribution networks through energy routers is also established.Finally,simulation results verify the effectiveness of the proposed planning model.Results show that peer-topeer energy transaction among distribution networks through energy routers can effectively reduce the comprehensive cost of distribution networks,significantly improve the power quality of the distribution networks,and reduce the impact of power fluctuation on the upstream grid incurred by the distribution network.

Polarization and wavelength routers based on difractive neural network

In the feld of information processing,all-optical routers are signifcant for achieving high-speed,high-capacity signal processing and transmission.In this study,we developed three types of structurally simple and fexible routers using the deep difractive neural network(D2 NN),capable of routing incident light based on wavelength and polarization.First,we implemented a polarization router for routing two orthogonally polarized light beams.The second type is the wavelength router that can route light with wavelengths of 1550,1300,and 1100 nm,demonstrating outstanding performance with insertion loss as low as 0.013 dB and an extinction ratio of up to 18.96 dB,while also maintaining excellent polarization preservation.The fnal router is the polarization-wavelength composite router,capable of routing six types of input light formed by pairwise combinations of three wavelengths(1550,1300,and 1100 nm)and two orthogonal linearly polarized lights,thereby enhancing the information processing capability of the device.These devices feature compact structures,maintaining high contrast while exhibiting low loss and passive characteristics,making them suitable for integration into future optical components.This study introduces new avenues and methodologies to enhance performance and broaden the applications of future optical information processing systems.

Design and Analysis of Prioritized Medium Access Control Protocol for Backbone Routers in Wireless Mesh Networks

A Prioritized Medium Access Control （P-MAC） protocol is proposed for wireless routers of mesh networks with quality-of-service provisioning. The simple yet effective design of P-MAC offers strict service differentiation for prioritized packets. A Markov model is developed to yield important performance matrices including the packet blocking probability due to queue overflow and the packet reneging probability due to delay bound. It is further proved that the service time of P-MAC approximates exponential distribution, and can be effectively estimated. The analytic models with preemptive and non-preemptive schemes, validated via simulations, show that P-MAC can effectively support traffic differentiation and achieve very low packet dropping （both reneging and blocking） probabilities when the traffic load is below the channel capacity. When the network is overloaded, P-MAC can still maintain extremely stable and high channel throughput. Moreover, it is demonstrated that P-MAC performs superior in multihop networks, further proving the advantages of the proposed protocol.

Diffserv AQM algorithm for edge and core routers

The existing active queue management （AQM） algorithm acts on subscribers and edge routers only, it does not support differentiate-serve （Diffserv） quality of service （QoS）, while the existing diffserv QoS has not considered the link capacities between edge routers and connected core routers. When a core router in a two layers’ network experiences congestion, the connected edge routers have no ability to adjust their access data rates. Thus, it is difficult to achieve the congestion control for the large scale network with many edge routers and core routers. To solve these problems, two difffserve AQM algorithms are proposed for the congestion control of multilayer network. One diffserv AQM algorithm implements fair link capacities of edge routers, and the other one implements unequal link capacities of edge routers, but it requires the core routers to have multi-queues buffers and Diffserv AQM to support. The proposed algorithms achieve the network congestion control by operating AQM parameters on the conditions of proposed three theorems for core and edge routers. The dynamic simulation results demonstrate the proposed control algorithms for core and edge routers to be valid.

RevivePath:Resilient Network-on-Chip Design Through Data Path Salvaging of Router

Network-on-Chip （NoC） with excellent scalability and high bandwidth has been considered to be the most promising communication architecture for complex integration systems. However, NoC reliability is getting continuously challenging for the shrinking semiconductor feature size and increasing integration density. Moreover, a single node failure in NoC might destroy the network connectivity and corrupt the entire system. Introducing redundancies is an efficient method to construct a resilient communication path. However, prior work based on redundancies, either results in limited reliability with coarse grain protection or involves even larger hardware overhead with fine grain. In this paper, we notice that data path such as links, buffers and crossbars in NoC can be divided into multiple identical parallel slices, which can be utilized as inherent redundancy to enhance reliability. As long as there is one fault-free slice left available, the proposed salvaging scheme named as RevivePath, can be employed to make the overall data path still functional. Furthermore, RevivePath uses the direct redundancy to protect the control path such as switch arbiter, routing computation, to provide a full fault-tolerant scheme to the whole router. Experimental results show that it achieves quite high reliability with graceful performance degradation even under high fault rate.

A low-power high-throughput link splitting router for NoCs

In this paper, we propose a technique for lowering the latency of the communication in a NoC （network on chip）. The technique, which can support two qualities of service （QoS）, i.e., the guaranteed throughput （GT） and best effort （BE）, is based on splitting a wider link into narrower links to increase throughput and decrease latency in the NoC. In addition, to ease the synchronization and reduce the crosstalk, we use the l-of-4 encoding for the smaller buses. The use of the encoding in the proposed NoC architecture considerably lowers the latency for both BE and GT packets. In addition, the bandwidth is increased while the power consumption of the links is reduced.

Analysis of a 32-Channal Benes Switching Network Including an SDM/WDM Router

An spatial division multiplexing/wavelength division multiplexing router is designed for applying in a fiber-optical wide area network. Our comparison shows various spans of the good SDM/WDM WAN using the SO A based router.

A High-Elasticity Router Architecture with Software Data Plane and Flow Switching Plane Separation

Routers have traditionally been architected as two elements: forwarding plane and control plane through For CES or other protocols. Each forwarding plane aggregates a fixed amount of computing, memory, and network interface resources to forward packets. Unfortunately, the tight coupling of packet-processing tasks with network interfaces has severely restricted service innovation and hardware upgrade. In this context, we explore the insightful prospect of functional separation in forwarding plane to propose a next-generation router architecture, which, if realized, can provide promises both for various packet-processing tasks and for flexible deployment while solving concerns related to the above problems. Thus, we put forward an alternative construction in which functional resources within a forwarding plane are disaggregated. A forwarding plane is instead separated into two planes: software data plane(SDP) and flow switching plane(FSP), and each plane can be viewed as a collection of "building blocks". SDP is responsible for packet-processing tasks without its expansibility restricted with the amount and kinds of network interfaces. FSP is in charge of packet receiving/transmitting tasks and can incrementally add switching elements, such as general switches, or even specialized switches, to provide network interfaces for SDP. Besides, our proposed router architecture uses network fabrics to achievethe best connectivity among building blocks,which can support for network topology reconfiguration within one device.At last,we make an experiment on our platform in terms of bandwidth utilization rate,configuration delay,system throughput and execution time.

A congestion-aware OE router employing fair arbitration for network-on-chip

To meet the demand for high on-chip network performance, flexible routing algorithms supplying path diversity and congestion alleviation are required. We propose a CAOE-FA router as a combination of congestionawareness and fair arbitration. Buffer occupancies from downstream neighbors are collected to indicate the congestion levels, among the candidate outputs permitted by the odd-even(OE) turn model, the lightest loaded direction is selected; fair arbitration is employed for the condition of the same congestion level to replace random selection. Experimental results show that the CAOE-FA can reduce the average packet latency by up to 22.18% and improve the network throughput by up to 68.58%, with ignorable price of hardware cost.

Area Analysis for On-chip Routers with Different Data-link Widths

Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can be used for NoCs. This paper focuses on the area costs for on-chip routers under four different data-link widths： 8 bits, 16 bits, 128 bits, and 256bits. Firstly, a virtual-channel based on-chip router is introduced. Secondly, the components of the router are implemented by Verilog HDL models and synthesized by Quartus II 4.0 in a FPGA device. Finally, the area costs are analyzed. It can be seen from the results that data-link width has great influence on area costs of buffers and crossbar while has no influence on area costs of arbiter.

An Efficient Network-on-Chip Router for Dataflow Architecture

Dataflow architecture has shown its advantages in many high-performance computing cases. In dataflow computing, a large amount of data are frequently transferred among processing elements through the network-on-chip （NoC）. Thus the router design has a significant impact on the performance of dataflow architecture. Common routers are designed for control-flow multi-core architecture and we find they are not suitable for dataflow architecture. In this work, we analyze and extract the features of data transfers in NoCs of dataflow architecture： multiple destinations, high injection rate, and performance sensitive to delay. Based on the three features, we propose a novel and efficient NoC router for dataflow architecture. The proposed router supports multi-destination; thus it can transfer data with multiple destinations in a single transfer. Moreover, the router adopts output buffer to maximize throughput and adopts non-flit packets to minimize transfer delay. Experimental results show that the proposed router can improve the performance of dataflow architecture by 3.6x over a state-of-the-art router.