SBH adjustment characteristic of the dopant segregation process for NiSi/n-Si SJDs

By means of analyzing theⅠ-Ⅴcharacteristic curve of NiSi/n-Si Schottkyjunction diodes（NiSi/n-Si SJDs）, abstracting the effective Schottky barrier height（φ_（B,eff）） and the idealfactor ofNiSi/n-Si SJDs and measuring the sheet resistance of NiSi films（R_（NiSi））,we study the effects of different dopant segregation process parameters,including impurity implantation dose,segregation annealing temperature and segregation annealing time,on theφ_（B,eff） of NiSi/ n-Si SJDs and the resistance characteristic of NiSi films.In addition,the changing rules ofφ_（B,eff） and R_（NiSi） are discussed.

Adjustment of NiSi/n-Si SBH by post-silicide of dopant segregation process

The post-silicide of dopant segregation process for adjusting NiSi/n-Si SBH（Schottky barrier height）is described.Adopting the analysis of the I–V characteristic curve and extrapolating the SBH of NiSi/n-Si Schottky junction diodes（NiSi/n-Si SJDs）,the effects of different of process parameters dopant segregation,including segregation anneal temperature and dopant implant dose,on the properties of the NiSi/n-Si SJDs have been studied,and the corresponding mechanisms are discussed.

杂质分凝技术对肖特基势垒高度的调制

为降低金属或金属硅化物源漏与沟道的肖特基势垒高度以改善肖特基势垒源漏场效应晶体管(SBSD-MOSFET)的开关电流比(Ion/Ioff),采用硅化诱发杂质分凝技术(SIDS)调节NiSi/n-Si肖特基二极管(NiSi/n-Si SJD)的肖特基势垒高度,系统地研究了SIDS工艺条件如杂质注入剂量、注入能量和硅化物形成工艺对肖特基势垒高度调节的影响。实验结果表明,适当增加BF2杂质的注入剂量或能量均能显著提高有效电子势垒高度(φBn,eff),也即降低了有效空穴势垒高度(φBp,eff),从而减小反向偏置漏电流。同时,与传统的一步退火工艺相比,采用两步退火工艺形成NiSi也有利于提高有效电子势垒高度,减小反向漏电流。最后,提出了一种优化的调制肖特基势垒高度的SIDS工艺条件。