Performance Tendency of Gain and Noise Figure at Different EDFA Configurations

A comprehensive behavioral investigation of gain and noise figure （NF） at different erbium doped fiber amplifier （EDFA） configurations is proposed. Configurations such as single pass （SP）, single pass with filter （SPF）, double pass （DP） and double pass with filter （DPF） are designed, investigated and compared. A continuous increasing of gain value is recorded by changing the configuration from SP to SPF to DP then to DPF. The NF value shows different behaviors at different configurations.

Design of a Low Power Low-Noise Amplifier with Improved Gain/Noise Ratio

This work details the development of a broad-spectrum LNA (Low Noise Amplifier) circuit using a 65 nm CMOS technology. The design incorporates an inductive degeneracy circuit, employing a theoretical approach to enhance gain, minimize noise levels, and uphold low power consumption. The progression includes a shift to a cascode structure to further refine LNA parameters. Ultimately, with a 1.8 V bias, the achieved performance showcases a gain-to-noise figure ratio of 16 dB/0.5 dB, an IIP3 linearity at 5.1 dBm, and a power consumption of 3 mW. This architecture is adept at operating across a wide frequency band spanning from 0.5 GHz to 6 GHz, rendering it applicable in diverse RF scenarios.

Research on optimizing the noise figure of low noise amplifier method via bias and frequency

In this paper, we present the design of an integrated low noise amplifier （LNA） for wireless local area network （WLAN） applications in the 5.15-5.825 GHz range using a SiGe BiCMOS technology. A novel method that can determine both the optimum bias point and the frequency point for achieving the minimum noise figure is put forward. The method can be used to determine the optimum impedance over a relevant wider operating frequency range. The results show that this kind of optimizing method is more suitable for the WLAN circuits design. The LNA gain is optimized and the noise figure （NF） is reduced. This method can also achieve the noise match and power match simultaneously. This proposal is applied on designing a LNA for IEEE 802.1 la WLAN. The LNA exhibits a power gain large than 16 dB from 5.15 to 5.825 GHz range. The noise figure is lower than 2 dB. The OIP3 is -8 dBm. Also the LNA is matched to 50 Ω input impedance with 6 mA DC current for differential design.

A 6-7 GHz,40 dB receiver RF front-end with 4.5 dB minimum noise figure in 0.13μm CMOS for IR-UWB applications

A wideband receiver RP front-end for IR-UWB applications is implemented in 0.13μm CMOS technology. Thanks to the direct sub-sampling architecture,there is no mixing process.Both LNA and VGA work at RF frequencies.To optimize noise as well as linearity,a differential common-source LNA with capacitive cross- coupling is used,which only consumes current of 1.8 mA from a 1.2 V power supply.Following LNA,a two-stage current-steering VGA is adopted for gain tuning.To extend the overall bandwidth,a three-stage staggered peaking technique is used.Measurement results show that the proposed receiver front-end achieves a gain tuning range from 5 to 40 dB within 6-7 GHz,a minimum noise figure of 4.5 dB and a largest IIP_3 of-11 dBm.The core receiver (without test buffer) consumes 14 mW from a 1.2 V power supply and occupies 0.58 mm^2 area.

A NOVEL SIMULTANEOUS NOISE AND INPUT VSWR MATCHING TECHNIQUE FOR BROADBAND LNA

The Simultaneous Noise and Input Voltage Standing Wave Ratio (VSWR) Matching (SNIM) condition for Low Noise Amplifier (LNA), in principle, can only be satisfied at a single fre-quency. In this paper, by analyzing the fundamental limitations of the narrowband SNIM technique for the broadband application, the authors present a broadband SNIM LNA systematic design technique. The designed LNA guided by the proposed methodology achieves 10 dB power gain with a low Noise Figure of 0.53 dB. Meanwhile, it provides wonderful input matching of 27 dB across the fre-quency range of 3～5 GHz. Therefore, broadband SNIM is realized.

Optimum Design for a Low Noise Amplifier in S-Band

An optimum design of a low noise amplifier （LNA） in S-band working at 2-4 GHz is described. Choosing FHC40LG high electronic mobility transistor （HEMT）, the noise figure of the designed amplifier simulated by Microwave Office is no more than 1.5 dB, meanwhile the gain is no less than 20 dB in the given bandwidth. The simulated results agree with the performance of the transistor itself well in consideration of its own minimum noise figure （0.3 dB） and associated gain （15.5 dB）. Simultaneously, the stability factor of the designed amplifier is no less than 1 in the given bandwidth.

Performance Enhancement of Praseodymium Doped Fiber Amplifiers

In this paper,we report a simulation study on the performance enhancement of Praseodymium doped silica fiber amplifiers(PDFAs)in O-band(1270-1350 nm)in terms of small signal gain,power conversion efficiency(PCE),and output optical power by employing bidirectional pumping.The PDFA performance is examined by optimizing the length of Praseodymium doped silica fiber(PDF),its mode-field diameter(MFD)and the concentration of Pr^(3+).A small-signal peak gain of 56.4 dB,power conversion efficiency(PCE)of 47%,and output optical power of around 1.6 W(32 dBm)is observed at optimized parameters for input signal wavelength of 1310 nm.Minimum noise figure(NF)of 4.1 dB is observed at input signal wavelength of 1310 nm.Moreover,the effect of varying the pump wavelength and pump power on output optical power of the amplifier and amplified spontaneous emission(ASE)noise is also investigated,respectively.Finally,the impact of ion-ion interaction(up-conversion effect)on small-signal gain of the amplifier is also studied by considering different values of up-conversion coefficient.

Nonlinear performances of dual-pump amplifiers in silicon waveguides

The performances of a dual-pump parametric and Raman amplification process and the wavelength conversion in silicon waveguides are investigated. By setting the Raman contribution fraction f to be 0.043 in our analytical model, the amplification gain of the probe signal can be obtained to be over 10 dB. The pump transfer noise （PTN）, the quantum noise （QN）, and the total noise figure （TNF） are discussed, and the TNF has a constant value of about 4 dB in the gain bandwidth. An idler signal generated during the parametric amplification （PA） process can be used to realize the wavelength conversion in wavelength division multiplexing （WDM） systems. In addition, the pump signal parameters, the generated free carrier lifetime and effective mode area （EMA） of the waveguide are analysed for the optimization of signal gain and noise characteristics.

A full W-band low noise amplifier module for millimeter-wave applications

A full W-band low noise amplifier （LNA） module is designed and fabricated. A broadband transition is introduced in this module. The proposed transition is designed, optimized based on the results from numerical simulations. The results show that 1 dB bandwidth of the transition ranges from 61 to 117 GHz. For the purpose of verification, two transitions in back-to-back connection are measured. The results show that transmission loss is only about 0.9-1.7 dB. This transition is used to interface integrated circuits to waveguide components. The characteristic of the LNA module is measured after assembly. It exhibits a broad bandwidth of 75 to 110 GHz, and has a small signal gain above 21 dB. The noise figure is lower than 5.2 dB throughout the entire W-band （below 3 dB from 89 to 95 GHz） at room temperature. The proposed LNA module exhibits potential for millimeter wave applications due to its high small signal gain, low noise, and low DC power consumption.

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier（LNA）,designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure（NF） of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point（IIP3） is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.

A 0.18μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter analysis and the details of circuit design are presented. The test chip was implemented in a TSMC 0.18 μm 1P4M RF CMOS process. The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz. The measured noise figure is around 1.5-1.7 dB on both bands. The LNA consumes less than 4.3 mA of current from a 1.8 V power supply. The measurement results show consistency with the design. And the LNA can fully satisfy the demands of the GNSS receiver.

A 2.4-GHz low power dual gain low noise amplifier for ZigBee

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.

A low noise CMOS RF front-end for UWB 6-9 GHz applications

An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented.A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB,an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of-12.6 dBm while in the low gain mode.This RF front-end consumes 17 mA from a 1.2 V supply voltage.

The effects of current density ratio and reflectivity on the gain,saturation and noise characteristics of a two-section MQW RSOA

A 1.3μm two-section multi-quantum well refective semiconductor optical amplifier is designed and fabricated. The impacts of injection current density ratio and the reflectivity of the reflective facet on gain, sat- uration and noise characteristics are studied theoretically and experimentally. The results indicate that the gain and saturation power can be easily manipulated by changing the current density ratio; and better gain and noise characteristics can be obtained when the reflectivity is appropriately selected.

A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz.The Gilbert mixer is known for its perfect port isolation and bad noise performance.The noise cancellation technique of LNA can be applied here to have a better NF.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz,an average noise figure of 5 dB and a minimum value of 4.3 dB.The core area is 0.6 x 0.45 mm;.

ESD-Induced Noise to Low Noise Amplifier Circuits in BiCMOS

Electrostatic discharge （ESD） induced parasitic effects have serious impacts on performance of radio frequency （RF） integrated circuits （IC）. This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures （NFs） of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier （LNA） circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.

Design of 2.1GHz CMOS Low Noise Amplifier

This paper discusses the design of a fully differential 2.1 GHz CMOS low noise amplifier using the TSMC 0.25 μm CMOS process. Intended for use in 3G, the low noise amplifier is fully integrated and without off-chip components. The design uses an LC tank to replace a large inductor to achieve a smaller die area, and uses shielded pad capacitances to improve the noise performance. This paper also presents evaluation results of the design.

Circuit Topology Analysis of CMOS LNA in Mobile Communication Systems

A Low Noise Amplifier (LNA) intended for the use in the front-end of the third-generation WCDMA receivers is designed in a standard 0 25?um CMOS process. In the LNA circuit, a positive-feedback Q-enhancement and tuning technique is used to obtain an optimal Q for acquiring a minimum noise figure. The LNA in our design has a forward gain of 20 3?dB and a minimum noise figure of 1 2?dB at 2 0?GHz. The power dissipation is 30?mW at a 2 5?V supply.

A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

A CMOS long-term evolution(LTE) direct convert receiver that eliminates the interstage SAW filter is presented.The receiver consists of a low noise variable gain transconductance amplifier(TCA),a quadrature passive current commutating mixer with a 25%duty-cycle LO,a trans-impedance amplifier(TIA),a 7th-order Chebyshev filter and programmable gain amplifiers(PGAs).A wide dynamic gain range is allocated in the RF and analog parts.A current commutating passive mixer with a 25%duty-cycle LO improves gain,noise,and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference.Fabricated in a 0.13μm CMOS process,the receiver chain achieves a 107 dB maximum voltage gain,2.7 dB DSB NF(from PAD port),-11 dBm 11P3,and>+65 dBm UP2 after calibration,96 dB dynamic control range with 1 dB steps,less than 2%error vector magnitude(EVM) from 2.3 to 2.7 GHz.The total receiver(total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

A high linearity SiGe HBT LNA for GPS receiver

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.