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High-performance amorphous In–Ga–Zn–O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO_(2) heterojunction charge trapping stack
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作者 熊文 霍景永 +3 位作者 吴小晗 刘文军 张卫 丁士进 《Chinese Physics B》 SCIE EI CAS CSCD 2023年第1期580-584,共5页
Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Co... Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention.Of the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase characteristics.The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 V.This is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction. 展开更多
关键词 nonvolatile memory a-IGZO thin-film transistor(TFT) charge trapping stack p-SnO/n-SnO_(2)heterojunction
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Low voltage program-erasable Pd-Al_2O_3-Si capacitors with Ru nanocrystals for nonvolatile memory application
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作者 蓝澜 苟鸿雁 +1 位作者 丁士进 张卫 《Chinese Physics B》 SCIE EI CAS CSCD 2013年第11期532-535,共4页
Pd-Al2O3-Si capacitors with Ru nanocrystals are fabricated and electrically characterized for nonvolatile memory application. While keeping the entire insulator Al2O3 thickness fixed, the memory window has a strong de... Pd-Al2O3-Si capacitors with Ru nanocrystals are fabricated and electrically characterized for nonvolatile memory application. While keeping the entire insulator Al2O3 thickness fixed, the memory window has a strong dependence on the tunneling layer thickness under low operating voltages, whereas it has weak dependence under high operating voltages. As for the optimal configuration comprised of 6-nm tunneling layer and 22-nm blocking layer, the resulting memory window increases from 1.5 V to 5.3 V with bias pulse increasing from 10-5 s to 10-2 s under ±7 V. A ten-year memory window as large as 5.2 V is extrapolated at room temperature after ±8 V/1 ms programming/erasing pulses. 展开更多
关键词 metal-oxide-semiconductor capacitors nonvolatile memory Ru nanocrystals atomic-layer-deposition
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Preparation of size controllable copper nanocrystals for nonvolatile memory applications
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作者 王利 孙红芳 +1 位作者 周惠华 朱静 《Chinese Physics B》 SCIE EI CAS CSCD 2010年第10期593-596,共4页
A method of fabricating Cu nanocrystals embedded in SiO2 dielectric film for nonvolatile memory applications by magnetron sputtering is introduced in this paper. The average size and distribution density of Cu nanocry... A method of fabricating Cu nanocrystals embedded in SiO2 dielectric film for nonvolatile memory applications by magnetron sputtering is introduced in this paper. The average size and distribution density of Cu nanocrystal grains are controlled by adjusting experimental parameters. The relationship between nanocrystal floating gate micro-structure and its charge storage capability is also discussed theoretically. 展开更多
关键词 nanocrystal grain nonvolatile memory Coulomb blockade effect magnetron sputtering
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Improved performance of Au nanocrystal nonvolatile memory by N2-plasma treatment on HfO2blocking layer
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作者 Chen Wang Yi-Hong Xu +5 位作者 Song-Yan Chen Cheng Li Jian-Yuan Wang Wei Huang Hong-Kai Lai Rong-Rong Guo 《Chinese Physics B》 SCIE EI CAS CSCD 2018年第6期410-414,共5页
The N2-plasma treatment on a HfO2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–Ta N/HfO2/Si ... The N2-plasma treatment on a HfO2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–Ta N/HfO2/Si O2/p-Si are also characterized. After N2-plasma treatment, the nitrogen atoms are incorporated into HfO2 film and may passivate the oxygen vacancy states. The surface roughness of HfO2 film can also be reduced. Those improvements of HfO2 film lead to a smaller hysteresis and lower leakage current density of the MOS capacitor. The N2-plasma is introduced into Au nanocrystal(NC) nonvolatile memory to treat the HfO2 blocking layer. For the N2-plasma treated device, it shows a better retention characteristic and is twice as large in the memory window than that for the no N2-plasma treated device. It can be concluded that the N2-plasma treatment method can be applied to future nonvolatile memory applications. 展开更多
关键词 Au nanocrystal nonvolatile memory N2-plasma HfO2 dielectric film.
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Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices
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作者 于杰 陈坤基 +5 位作者 马忠元 张鑫鑫 江小帆 吴仰晴 黄信凡 Shunri Oda 《Chinese Physics B》 SCIE EI CAS CSCD 2016年第9期518-522,共5页
Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal(Si-NC) nonvolatile memory(NVM) devices for its scaling down limit.In this work,we... Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal(Si-NC) nonvolatile memory(NVM) devices for its scaling down limit.In this work,we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor(CMOS) technology.It is found that the memory windows of eight kinds of test key cells are almost the same of about1.64 V @ ±7 V/1 ms,which are independent of the gate area,but mainly determined by the average size(12 nm) and areal density(1.8×10^(11)/cm^2) of Si-NCs.The program/erase(P/E) speed characteristics are almost independent of gate widths and lengths.However,the erase speed is faster than the program speed of test key cells,which is due to the different charging behaviors between electrons and holes during the operation processes.Furthermore,the data retention characteristic is also independent of the gate area.Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. 展开更多
关键词 silicon nanocrystals nonvolatile memory scaling dependence different charging behaviors
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Borophene-ZnO heterostructures:Preparation and application as broadband photonic nonvolatile memory
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作者 Runsheng Liu Chuang Hou +2 位作者 Xinchao Liang Zitong Wu Guoan Tai 《Nano Research》 SCIE EI CSCD 2023年第4期5826-5833,共8页
High-performance photonic nonvolatile memory which combines data storage and photosensing can achieve low power consumption and ensure computational energy efficiency.Heterostructure has been theoretically and experim... High-performance photonic nonvolatile memory which combines data storage and photosensing can achieve low power consumption and ensure computational energy efficiency.Heterostructure has been theoretically and experimentally proved to have synergistic effects between two materials,which can lead to promising electronic and optical properties for advanced optoelectronic devices.Herein,we report the preparation of borophene-ZnO heterostructures and their applications of broadband photonic nonvolatile memory.The memory shows a good switching ratio(5×10^(3))and long-term stability(3,600 s),which are superior to those of the pristine borophene or ZnO quantum dots(QDs).It is found that the memory shows a broad light response from ultraviolet(365 nm)to near infrared(850 nm).Besides,the SET voltage will decrease when the device is exposed to light,which can be attributed to the separation of holes and electrons in accelerating the formation of vacancy conductive filament.This work not only provides a promising material for next-generation photoelectric information,but also paves the way for borophene-based memory towards data storage devices. 展开更多
关键词 borophene ZNO HETEROSTRUCTURE photoluminescence(PL)quenching nonvolatile memory light control
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Ferroelectric-gated ReS_(2)field-effect transistors for nonvolatile memory 被引量:2
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作者 Li Liu Hao Wang +7 位作者 Qilong Wu Kang Wu Yuan Tian Haitao Yang Cheng Min Shen Lihong Bao Zhihui Qin Hong-Jun Gao 《Nano Research》 SCIE EI CSCD 2022年第6期5443-5449,共7页
Ferroelectric field-effect transistors(FeFET)with nondestructive readout capability have emerged as an attractive candidate for next-generation nonvolatile memory technology.Herein,we demonstrate ferroelectric-gated n... Ferroelectric field-effect transistors(FeFET)with nondestructive readout capability have emerged as an attractive candidate for next-generation nonvolatile memory technology.Herein,we demonstrate ferroelectric-gated nonvolatile memory featuring a top gate architecture by combining multi-layer ReS_(2)with ferroelectric poly(vinylidene fluoride-trifluoroethylene)(P(VDF-TrFE))copolymer films.The ReS_(2)FeFET using hBN as substrate shows a large memory window of~30 V.Repeated write/erase operations are successfully performed by applying pulse voltage of±25 V with 1 ms width to the ferroelectric P(VDF-TrFE),and an ultra-high write/erase ratio of~107 can be achieved.Furthermore,the ReS_(2)FeFET shows stable data retention capability of longer than 2,000 s and reliable endurance of greater than 2,000 cycles.These characteristics highlight that such ferroelectricgated nonvolatile memory has great potential in future non-volatile memory applications. 展开更多
关键词 FERROELECTRIC nonvolatile memory poly(vinylidene fluoride-trifluoroethylene)(P(VDF-TrFE)) ReS_(2)
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Density-controllable nonvolatile memory devices having metal nanocrystals through chemical synthesis and assembled by spin-coating technique 被引量:1
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作者 王广利 陈裕斌 +4 位作者 施毅 濮林 潘力嘉 张荣 郑有炓 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第12期70-74,共5页
A novel two-step method is employed, for the first time, to fabricatc nonvolatile memory devices that have metal nanoerystals. First, size-averaged Au nanocrystals are synthesized chemically; second, they are assemble... A novel two-step method is employed, for the first time, to fabricatc nonvolatile memory devices that have metal nanoerystals. First, size-averaged Au nanocrystals are synthesized chemically; second, they are assembled into memory devices by a spin-coating technique at room temperature. This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually. In addition, processes at room temperature prevent Au diffusion, which is a main concem for the application of metal nanocrystal-based memory. The experimental results, both the morphology characterization and the electrical measurements, reveal that there is an optimum density of nanocrystal monolayer to balance between long data retention and a large hysteresis memory window. At the same time, density-controllable devices could also feed the preferential emphasis on either memory window or retention time. All these facts confirm the advantages and novelty of our two-step method. 展开更多
关键词 metal nanocrystal nonvolatile memory SELF-ASSEMBLE spin-coating technique conductance--voltagecurve memory window
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A low temperature processed Si-quantum-dot poly-Si TFT nonvolatile memory device
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作者 孙玮 《Journal of Semiconductors》 EI CAS CSCD 2013年第6期77-80,共4页
This paper reports on a successful demonstration of poly-Si TFT nonvolatile memory with a much reduced thermal-budget.The TFT uses uniform Si quantum-dots(size -10 nm and density -10-(11) cm-(-2)) as storage med... This paper reports on a successful demonstration of poly-Si TFT nonvolatile memory with a much reduced thermal-budget.The TFT uses uniform Si quantum-dots(size -10 nm and density -10-(11) cm-(-2)) as storage media,obtained via LPCVD by flashing SiH4/H2 at 580℃for 15 s on a Si3N4 surface.The poly-Si grain-enlargement step was shifted after source/drain formation.The NiSix-silicided source/drain enables a fast lateral-recrystallization,and thus grain-enlargement can be accomplished by a much reduced thermal-cycle(i.e., 550℃/4 h).The excellent memory characteristics suggest that the proposed poly-Si TFT Si quantum-dot memory and associated processes are promising for use in wider TFT applications,such as system-on-glass. 展开更多
关键词 poly-silicon TFT nonvolatile memory low-thermal-budget metal-induced lateral crystallization Siquantum-dots
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Formation of stacked ruthenium nanocrystals embedded in SiO_2 for nonvolatile memory applications
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作者 毛平 张志刚 +2 位作者 潘立阳 许军 陈培毅 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2009年第9期9-12,共4页
Two methods are proposed to fabricate stacked ruthenium (Ru) nanocrystals (NCs): rapid thermal annealing (RTA) for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density o... Two methods are proposed to fabricate stacked ruthenium (Ru) nanocrystals (NCs): rapid thermal annealing (RTA) for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2-4 nm and 3 × 10^12 cm^-2 for the former method, compared to 3-7 nm and 2 ×10^12 cm^-2 for the latter. Because of the higher surface trap density and more uniform electron tunneling path between upper and lower Ru NCs, a 5.2 V memory window and 1 V after a period of 10 years are observed in metal oxide semiconductor (MOS) capacitors fabricated by the former method, which are much better than 4.6 V and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology. 展开更多
关键词 ruthenium nanocrystal stacked FORMATION nonvolatile memory
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Performance and Reliability of Multilayer Silicon Nanocrystal Nonvolatile Memory
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作者 王柳笛 张志刚 +2 位作者 赵悦 毛平 潘立阳 《Tsinghua Science and Technology》 SCIE EI CAS 2009年第1期103-105,共3页
Nonvolatile memories (NVMs) with triple layers of silicon nanocrystals were fabricated with conventional CMOS technology. This paper explores the program/erase performance and reliability of NVMs with three layers o... Nonvolatile memories (NVMs) with triple layers of silicon nanocrystals were fabricated with conventional CMOS technology. This paper explores the program/erase performance and reliability of NVMs with three layers of nanocrystais. The results indicate that the nanocrystals in the triple-layer nanocrystal NVM (NCNVM) are difficult to fully charge during the programming process. The programming speed of the triple-layer NCNVMs is quicker than that of single-layer NCNVMs, which means that the second and third layers of nanocrystals in the triple-layer NCNVM affect the charge of the first layer nanocrystals. Reliability tests show that the memory window has little degradation after 1× 10^4 cycles. 展开更多
关键词 nanocrystal nonvolatile memory program and erase ENDURANCE
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Surface-type nonvolatile electric memory elements based on organic-on-organic CuPc-H_2Pc heterojunction
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作者 Khasan S.Karimov Zubair Ahmad +3 位作者 Farid Touati M.Mahroof-Tahir M.Muqeet Rehman S.Zameer Abbas 《Chinese Physics B》 SCIE EI CAS CSCD 2015年第11期328-332,共5页
A novel surface-type nonvolatile electric memory elements based on organic semiconductors CuPc and H2Pc are fabricated by vacuum deposition of the CuPc and H2Pc films on preliminary deposited metallic (Ag and Cu) el... A novel surface-type nonvolatile electric memory elements based on organic semiconductors CuPc and H2Pc are fabricated by vacuum deposition of the CuPc and H2Pc films on preliminary deposited metallic (Ag and Cu) electrodes. The gap between Ag and Cu electrodes is 3040μm. For the current-voltage (I-V) characteristics the memory effect, switching effect, and negative differential resistance regions are observed. The switching mechanism is attributed to the electric-field-induced charge transfer. As a result the device switches from a low to a high-conductivity state and then back to a low conductivity state if the opposite polarity voltage is applied. The ratio of resistance at the high resistance state to that at the low resistance state is equal to 120-150. Under the switching condition, the electric current increases -- 80-100 times. A comparison between the forward and reverse I-V characteristics shows the presence of rectifying behavior. 展开更多
关键词 heterojunction nonvolatile memory organic-on-organic CUPC H2Pc
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Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-κ Dielectrics and SiGe Epitaxial Substrates
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作者 Zhao-Zhao Hou Gui-Lei Wang +4 位作者 Jin-Juan Xiang Jia-Xin Yao Zhen-Hua Wu Qing-Zhu Zhang Hua-Xiang Yin 《Chinese Physics Letters》 SCIE CAS CSCD 2017年第9期95-99,共5页
A novel high-κ~ A1203/HfO2/AI203 nanolaminate charge trapping memory capacitor structure based on SiGe substrates with low interface densities is successfully fabricated and investigated. The memory capacitor exhibit... A novel high-κ~ A1203/HfO2/AI203 nanolaminate charge trapping memory capacitor structure based on SiGe substrates with low interface densities is successfully fabricated and investigated. The memory capacitor exhibits excellent program-erasable characteristics. A large memory window of ~4 V, a small leakage current density of ~2 ×10-6 Acre-2 at a gate voltage of 7V, a high charge trapping density of 1.42 × 1013 cm-2 at a working vo]tage of 4-10 V and good retention characteristics are observed. Furthermore, the programming (△ VFB = 2.8 V at 10 V for 10μs) and erasing speeds (△VFB =-1.7 V at -10 V for 10μs) of the fabricated capacitor based on SiGe substrates are significantly improved as compared with counterparts reported earlier. It is concluded that the high-κ Al2O3/HfO2/Al2O3 nanolaminate charge trapping capacitor structure based on SiGe substrates is a promising candidate for future nano-scaled nonvolatile flash memory applications. 展开更多
关键词 Dielectrics and SiGe Epitaxial Substrates Improved Operation Characteristics for nonvolatile Charge-Trapping memory Capacitors with High
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New‑Generation Ferroelectric AlScN Materials
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作者 Yalong Zhang Qiuxiang Zhu +1 位作者 Bobo Tian Chungang Duan 《Nano-Micro Letters》 SCIE EI CAS CSCD 2024年第11期88-118,共31页
Ferroelectrics have great potential in the field of nonvolatile memory due to programmable polarization states by external electric field in nonvolatile manner.However,complementary metal oxide semiconductor compatibi... Ferroelectrics have great potential in the field of nonvolatile memory due to programmable polarization states by external electric field in nonvolatile manner.However,complementary metal oxide semiconductor compatibility and uniformity of ferroelectric performance after size scaling have always been two thorny issues hindering practical application of ferroelectric memory devices.The emerging ferroelectricity of wurtzite structure nitride offers opportunities to circumvent the dilemma.This review covers the mechanism of ferroelectricity and domain dynamics in ferroelectric AlScN films.The performance optimization of AlScN films grown by different techniques is summarized and their applications for memories and emerging in-memory computing are illustrated.Finally,the challenges and perspectives regarding the commercial avenue of ferroelectric AlScN are discussed. 展开更多
关键词 AlScN FERROELECTRICS nonvolatile memory In-memory computing
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Improvement of Electrical Properties of the Ge2Sb2Te5 Film by Doping Si for Phase-Change Random Access Memory 被引量:2
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作者 乔保卫 冯洁 +5 位作者 赖云锋 凌云 林殷茵 汤庭鳌 蔡炳初 陈邦明 《Chinese Physics Letters》 SCIE CAS CSCD 2006年第1期172-174,共3页
Si-doped Ge2Sb2Te5 films have been prepared by dc magnetron co-sputtering with Ge2Sb2Te5 and Si targets. The addition of Si in the Ge2Sb2Te5 film results in the increase of both crystallization temperature and phasetr... Si-doped Ge2Sb2Te5 films have been prepared by dc magnetron co-sputtering with Ge2Sb2Te5 and Si targets. The addition of Si in the Ge2Sb2Te5 film results in the increase of both crystallization temperature and phasetransition temperature from face-centred-cubic (fcc) phase to hexagonal (hex) phase. The resistivity of the Ge2Sb2Te5 film shows a significant increase with the Si doping. When doping 11.8 at.% of Si in the film, the resistivity after 460℃ annealing increases from 1 to 11 mΩ.cm and dynamic resistance increase from 64 to 99Ω compared to the undoped Ge2Sb2Te5 film. This is very helpful to writing current reduction of phase-change random access memory. 展开更多
关键词 nonvolatile memory THIN-FILMS RESISTANCE ALLOYS
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Design and Analysis of Low Power Hybrid Memristor-CMOS Based Distinct Binary Logic Nonvolatile SRAM Cell 被引量:1
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作者 Veerappan Saminathan Kuppusamy Paramasivam 《Circuits and Systems》 2016年第3期119-127,共9页
Memristor is a newly found fourth circuit element for the next generation emerging nonvolatile memory technology. In this paper, design of new type of nonvolatile static random access memory cell is proposed by using ... Memristor is a newly found fourth circuit element for the next generation emerging nonvolatile memory technology. In this paper, design of new type of nonvolatile static random access memory cell is proposed by using a combination of memristor and complemented metal oxide semiconductor. Biolek memristor model and CMOS 180 nm technology are used to form a single cell. By introducing distinct binary logic to avoid safety margin is left for each binary logic output and enables better read/write data integrity. The total power consumption reduces from 0.407 mw (milli-watt) to 0.127 mw which is less than existing memristor based memory cell of the same CMOS technology. Read and write time is also significantly reduced. However, write time is higher than conventional 6T SRAM cell and can be reduced by increasing motion of electron in the memristor. The change of the memristor state is shown by applying piecewise linear input voltage. 展开更多
关键词 Memristor-CMOS nonvolatile memory Power Consumption DBL PWL Input
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Resistive random access memory and its applications in storage and nonvolatile logic 被引量:2
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作者 Dongbin Zhu Yi Li +3 位作者 Wensheng Shen Zheng Zhou Lifeng Liu Xing Zhang 《Journal of Semiconductors》 EI CAS CSCD 2017年第7期18-30,共13页
The resistive random access memory(RRAM) device has been widely studied due to its excellent memory characteristics and great application potential in different fields. In this paper, resistive switching materials,s... The resistive random access memory(RRAM) device has been widely studied due to its excellent memory characteristics and great application potential in different fields. In this paper, resistive switching materials,switching mechanism, and memory characteristics of RRAM are discussed. Recent research progress of RRAM in high-density storage and nonvolatile logic application are addressed. Technological trends are also discussed. 展开更多
关键词 RRAM memory nonvolatile logic metal–oxide resistive switching
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Ferromagnetic and ferroelectric two-dimensional materials for memory application 被引量:4
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作者 Zhen Liu Longjiang Deng Bo Peng 《Nano Research》 SCIE EI CAS CSCD 2021年第6期1802-1813,共12页
The discoveries of ferromagnetic and ferroelectric two-dimensional(2D)materials have dramatically inspired intense interests due to their potential in the field of spintronic and nonvolatile memories.This review focus... The discoveries of ferromagnetic and ferroelectric two-dimensional(2D)materials have dramatically inspired intense interests due to their potential in the field of spintronic and nonvolatile memories.This review focuses on the latest 2D ferromagnetic and ferroelectric materials that have been most recently studied,including insulating ferromagnetic,metallic ferromagnetic,antiferromagnetic and ferroelectric 2D materials.The fundamental properties that lead to the long-range magnetic orders of 2D materials are discussed.The low Curie temperature(Tc)and instability in 2D systems limits their use in practical applications,and several strategies to address this constraint are proposed,such as gating and composition stoichiometry.A van der Waals(vdW)heterostructure comprising 2D ferromagnetic and ferroelectric materials will open a door to exploring exotic physical phenomena and achieve multifunctional or nonvolatile devices. 展开更多
关键词 two-dimensional(2D)materials FERROMAGNETIC FERROELECTRIC HETEROSTRUCTURE nonvolatile memory
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Sub-femto-Joule energy consumption memory device based on van der Waals heterostructure for in-memory computing 被引量:2
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作者 Zi-Jia Su Zi-Hao Xuan +3 位作者 Jing Liu Yi Kang Chun-Sen Liu Cheng-Jie Zuo 《Chip》 2022年第2期35-42,共8页
In-memory computing has carried out calculations in situ within each memory unit and its main power consumption comes from data writ-ing and erasing.Further improvements in the energy efficiency of in-memory computing... In-memory computing has carried out calculations in situ within each memory unit and its main power consumption comes from data writ-ing and erasing.Further improvements in the energy efficiency of in-memory computing require memory devices with sub-femto-Joule energy consumption.Floating gate memory devices based on two-dimensional(2D)material heterostructures have outstanding char-acteristics such as non-volatility,multi-bit storage,and low opera-tion energy,suitable for application in in-memory computing chips.Here,we report a floating gate memory device based on a WSe 2/h-BN/Multilayer-graphene/h-BN heterostructure,the energy consump-tion of which is in sub-femto Joule(0.6 fJ)per operation for pro-gram/erase,and the read power consumption is in the tens of femto Watt(60 fW)range.We show a Hopfield neural network composed of WSe 2/h-BN/Multilayer-graphene/h-BN heterostructure floating gate memory devices,which can recall the original patterns from incorrect patterns.These results shed light on the development of future com-pact and energy-efficient hardware for in-memory computing sys-tems. 展开更多
关键词 two-dimensional material heterostructures nonvolatile memory energy consumption sub-femto-Joule
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BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories
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作者 Jishen Zhao Cong Xu +1 位作者 Tao Zhang Yuan Xie 《Journal of Computer Science & Technology》 SCIE EI CSCD 2016年第1期20-35,共16页
Limited main memory bandwidth is becoming a fundamental performance bottleneck in chipmultiprocessor (CMP) design. Yet directly increasing the peak memory bandwidth can incur high cost and power consumption. In this... Limited main memory bandwidth is becoming a fundamental performance bottleneck in chipmultiprocessor (CMP) design. Yet directly increasing the peak memory bandwidth can incur high cost and power consumption. In this paper, we address this problem by proposing a memory, a bandwidth-aware reconfigurable cache hierarchy, BACH, with hybrid memory technologies. Components of our BACH design include a hybrid cache hierarchy, a reconfiguration mechanism, and a statistical prediction engine. Our hybrid cache hierarchy chooses different memory technologies with various bandwidth characteristics, such as spin-transfer torque memory (STT-MRAM), resistive memory (ReRAM), and embedded DRAM (eDRAM), to configure each level so that the peak bandwidth of the overall cache hierarchy is optimized. Our reconfiguration mechanism can dynamically adjust the cache capacity of each level based on the predicted bandwidth demands of running workloads. The bandwidth prediction is performed by our prediction engine. We evaluate the system performance gain obtained by BACH design with a set of multithreaded and multiprogrammed workloads with and without the limitation of system power budget. Compared with traditional SRAM-based cache design, BACH improves the system throughput by 58% and 14% with multithreaded and multiprogrammed workloads respectively. 展开更多
关键词 memory bandwidth hybrid cache reconfigurable cache nonvolatile memory
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