Design of MCI single and symmetrical on-chip spiral inductors

In this paper,the MCI（multipath crossover interconnection）technique for octagon single and symmetrical spiral inductors has been presented to improve the quality factor.The metal wires of the single and symmetrical inductors formed by the top metal are divided into multiple segments according to the depth of the skin effects.The outermost path of the metal is crossover-interconnected to the innermost path by the underlayer metal and via The crossover technique makes the lengths of the total current paths between two ports approximately equal to each other.Therefore,the induced magnetic flux and resistance of each path can be balanced and the Q-factor of spiral inductors can be enhanced.The proposed MCI technique has been validated by the electromagnetic simulation with the 130-nm 1P6M SiGe BiCMOS process.For the devices with occupying areas of 240 240 μm^2,results of electromagnetic simulation show that about 24%improvement in the Q-peak（3.3 GHz）of the MCI single inductor as compared to conventional single inductors（3.1 GHz）,and about 88.1%improvement in the Q-peak（3.2 GHz）of the MCI symmetrical inductor as compared to conventional symmetrical inductors（1.8 GHz）.

Double-πfully scalable model for on-chip spiral inductors

A novel double-n equivalent circuit model for on-chip spiral inductors is presented. A hierarchical structure, similar to that of MOS models is introduced. This enables a strict partition of the geometry scaling in the global model and the model equations in the local model. The major parasitic effects, including the skin effect, the proximity effect, the inductive and capacitive loss in the substrate, and the distributed effect, are analytically calculated with geometric and process parameters in the locaMevel. As accurate values of the layout and process parameters are difficult to obtain, a set of model parameters is introduced to correct the errors caused by using these given inaccurate layout and process parameters at the local level. Scaling rules are defined to enable the formation of models that describe the behavior of the inductors of a variety of geometric dimensions. A series of asymmetric inductors with different geometries are fabricated on a standard 0.18-μm SiGe BiCMOS process with 100 Ω/cm substrate resistivity to verify the proposed model. Excellent agreement has been obtained between the measured results and the proposed model over a wide frequency range.

A 2.4GHz CMOS Quadrature Voltage-Controlled Oscillator Based on Symmetrical Spiral Inductors and Differential Diodes

A voltage controlled oscillator (VCO) which can generate 2 4GHz quadrature local oscillating (LO) signals is reported.It combines a LC VCO,realized by on chip symmetrical spiral inductors and differential diodes,and a two stage ring VCO.The principle of this VCO is demonstrated and further the phase noise is discussed in detail.The fabrication of prototype is demonstrated using 0 25μm single poly five metal N well salicide CMOS digital process.The reports show that the novel VCO is can generate quadrature LO signals with a tuning range of more than 300MHz as well as the phase noise--104 33dBc/Hz at 600KHz offset at 2 41GHz (when measuring only one port of differential outputs).In addition,this VCO can work in low power supply voltage and dissipate low power,thus it can be used in many integrated transceivers.

Parameter Extraction for 2-π Equivalent Circuit Model of RF CMOS Spiral Inductors

A novel parameter extraction method with rational functions is presented for the 2-πequivalent circuit model of RF CMOS spiral inductors. The final S-parameters simulated by the circuit model closely match experimental data. The extraction strategy is straightforward and can be easily implemented as a CAD tool to model spiral inductors. The resulting circuit models will be very useful for RF circuit designers.

Fabrication of Meander and Spiral Type Micro Inductors

To obtain microstructure of magnetic devices, the thin film inductors were fabricated by the process such as thin film manufacturing, photolithography and wet etching. The frequency characteristics of these devices are measured at high frequency range. When the inductor sizes of the spiral and the meander type are same, the inductance and the quality factor of the spiral type inductor are larger than those of the meander type inductor, but the driving frequency of the spiral type inductor is lower than that of the meander type inductor.

The coupling effect of air-bridges on broadband spiral inductors in SiC-based MMIC technology

The coupling effect of air-bridges on broadband spiral inductors in SiC-based MMIC technology has been investigated deeply. The fabricated 1-nH spiral inductor on SiC substrate demonstrates a self-resonant frequency of 51.6 GHz, with a peak Q-fact of 12.14 at 22.1 GHz. From the S-parameters measurements, the exponential decay phenomenon is observed for L, Q-factor, and SRF with the air-bridge height decreasing, and an analytic expression is concluded to exactly fit the measured data which can be used to predict the performance of the spiral inductor. All the coefficients in the formula have specific meaning. By means of establishing the lumped model, the parasitic coupling capacitance of the air-bridge has been extracted and presents the exponential decay with the air-bridge heights decreasing which indicates that this capacitor is directly related to the coupling effect of the air-bridge. Through the electromagnetic field distribution simulation, the details of the electric field around the air-bridge have been presented which demonstrate the formation and the variation principles of the coupling effect.

Fabrication and Performance of Novel RF Spiral Inductors on Silicon

This paper discusses fabrication and performance of novel circular spiral inductors on silicon. The substrate materials underneath the inductor coil are removed by wet etching process. In the fabrication process, fine polishing of the photoresist is used to simplify the processes and ensure perfect contact between the seed layer and the top of pillars. Dry etching technique is used to remove the seed layer. The results show that Q-factor of the inductor is greatly improved by removing silicon underneath the inductor coil. The spiral inductor with line width of 50 μm has a peak Q-factor of 10 for the inductance of 2.5 nH at frequency of 1 GHz, and the resonance frequency of the inductor is about 8.5 GHz. For the inductor of conductor width 80 μm, the peak Q-factor increases to about 17 for inductance of 1.5 nH in the frequency range of 0.05 -3.00 GHz.

Layout Design and Optimization of RF Spiral Inductors on Silicon Substrate

The effects of key geometrical parameters on the performance of integrated spiral inductors are investigated with the 3D electromagnetic simulator HFSS.While varying geometrical parameters such as the number of turns(N),the width of the metal traces(W),the spacing between the traces(S),and the inner diameter(ID),changes in the performance of the inductors are analyzed in detail.The reasons for these changes in performance are presented.Simulation results indicate that the performance of an integrated spiral inductor can be improved by optimizing its layout.Some design rules are summarized.

The Application of FDTD and Micro Genetic Algorithms on the Planar Spiral Inductors

High Q inductors are the important elements for RF circuit design. In this paper, the FDTD method is applied to explain the crowding effect of the spiral inductor , which can never be accurately analyzed by analytical solutions. The experimental results verify the FDTD simulation. The micro genetic algorithms and FDTD are combined to design the high Q of the inductor, the results show the efficiency of this exploration.

Performance Analysis of RF Spiral Inductor with Gradually Changed Metal Width and Space

To decrease the metal losses of RF spiral inductor,a novel layout structure with gradually reduced metal line width and space from outside to inside is presented. This gradual changed inductor has less eddy-current effect than the conventional inductor of fixed metal width and space. So the series resistance can be reduced and the quality （Q） factor of the inductor relating to metal losses is increased. The obtained experimental results corroborate the validity of the proposed method. For a 6nH inductor on high-resistivity silicon at 2.46GHz,Q factor of 14.25 is 11.3% higher than the conventional inductor with the same layout size. This inductor can be integrated with radio frequency integrated circuits to gain better performance in RF front end of a wireless communication system.

A Novel Lateral Solenoidal On-Chip Integrated Inductor Implemented in Conventional Si Process

A new structure of the on- chip integrated inductors im plem ented in conventional Si process is presented as a lateral solenoid.The fabrication process utilizes a conventional Si technology with standard double- layer m etal- lization.S param eters of the inductors based equivalent circuit are investigated and the inductor parameters are cal- culated from the m easured data.Experimental results are presented on an integrated inductors fabricated in a lateral solenoid type utilizing double m etal layers rather than a single metal layer as used in conventional planar spiral de- vices.Inductors with peak Q of 1.3and inductance value of 2 .2 n H are presented,which are com parable to conven- tional planar spiral inductors.

Patterned Dual pn Junctions Restraining Substrate Loss of an On-Chip Inductor

Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.

MEMS Inductor Consisting of Suspended Thick Crystalline Silicon Spiral with Copper Surface Coating

A novel MEMS inductor consisting of a planar single crystalline silicon spiral with a copper surface coating as the conductor is presented. Using a silicon-glass anodic bonding and deep etching formation-and-release process,a 40μm-thick silicon spiral is formed, which is suspended on a glass substrate to eliminate substrate loss. The surfaces of the silicon spiral are coated with highly conformal copper by electroless plating to reduce the resis- tive loss in the conductor,with thin nickel film plated on the surface of the copper layer for final surface passivation. The fabricated inductor exhibits a self-resonance frequency higher than 15GHz,with a quality factor of about 40 and an inductance of over 5nil at 11.3GHz. Simulations based on a compact equivalent circuit model of the inductor and parameter extraction using a characteristic-function approach are carried out,and good agreement with measurements is obtained.

Lumped Equivalent Circuit of Planar Spiral Inductor for CMOS RFIC Application

A lumped π-type equivalent circuit of planar spiral inductor for CMOS RFIC application is developed by the domain decomposition method for conformal modules （DDM-CM）. Closed form expressions of lumped parameters for a square spiral inductor on a Si-SiO2 substrate are obtained and verified with the previously published experimental results.

On-Chip Inductor Technique for Improving LNA Performance Operating at 15 GHz

This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.

Simplified Model of a Layer of Interconnects under a Spiral Inductor

An empirical effective medium approximation that provides a homogeneous equivalent for a layer of interconnects un-derneath a spiral inductor is presented. When used as part of a numerical 3D model of the inductor, this approach yields a faster simulation that uses less memory, yet still predicts the quality factor and inductance to within 1%. We expect this technique to find use in the electromagnetic modeling of System-on-Chip.

A Fundamental Approach for Design and Optimization of a Spiral Inductor

This technical paper presents a fundamental approach for design and optimization of a spiral inductor using ASITIC(analysis and simulation of spiral inductors and transformers for ICs)and SpiralCalc(integrated spiral inductor calculator).Both tools are available for research and non-commercial purposes.Inductors are key components esp.for impedance matching and are designed such that they would exhibit a high Q-factor(quality-factor)for the specific inductance and frequency range of operation.A sample value of 5.3 nH is set for this paper for the spiral inductor design using the tools.For optimum Q-factor,an octagonal geometry for spiral inductor is used for ASITIC design,to have a close comparison to that of the SpiralCalc.Design methodologies for the optimization of the spiral inductor parameters such as the inductance and the Q-factor are discussed.Results comparison between the two tools is also presented.Design tradeoffs between inductor parameters are inevitable,and these parameters affect the performance of the inductor esp.at higher frequencies.With this,it is crucial that inductors be designed carefully for their effective frequency range of operation and specific requirements of the intended application.

基于水性功能油墨的气溶胶喷印工艺的研究及应用

气溶胶喷印水性功能油墨能为微纳柔性电子技术提供更环保的解决方案,但在油墨特性及复杂的打印参数共同作用下,其打印连续性、迹线成形、过度喷涂方面的缺陷亟待解决。基于聚乙烯吡咯烷酮(PVP)水性油墨,通过控制变量法系统地探究了适用于气溶胶喷印的水性油墨黏度(1~10 mPa·s)并优化了喷印工艺,总结出水性油墨黏度与气溶胶喷印的最优参数范围设置规律,并据此进行了水性纳米银油墨的喷印,制备了外径为1.96 mm的平面螺旋电感,表征了其电感及品质因数,测试结果与仿真结果有良好的一致性,其电感在0.024μH左右,可应用于射频识别(RFID)、滤波以及感应元件等领域。该结果为气溶胶喷印水性功能油墨的研究提供了前期的实验支持,有望推动气溶胶喷印在微纳柔性电子技术中的发展。

Analysis of substrate eddy effects and distribution effects in silicon-based inductor model

The concepts of substrate eddy influence factor and distribution-effects-occurring frequency are presented. The effects of substrate resistivity and inductor spiral length on the substrate eddy and distribution effects are captured. The substrate eddy influence factors of an inductor （6 turn, 3 060 μm in length） fabricated on low （ 1 Ω. cm） and high resistivity（ 1 000 Ω.cm） silicon substrates are 0. 3 and 0. 04, and the distribution-effects- occurring frequencies are 1.8 GHz and 14. 5 GHz, respectively. The measurement results show that the equivalent circuit model of the inductor on low resistivity silicon must take into consideration substrate eddy effects and distribution effects. However, the circuit model of the inductor on high resistivity silicon cannot take into account the substrate eddy effects and the distribution effects at the frequencies of interest. Its simple model shows agreement with the measurements, and the contrast is within 7%.

Scalable modeling and comparison for spiral inductors using enhanced 1-π and 2-π topologies

Two different scalable models developed based on enhanced 1-πand 2-πtopologies are presented for onchip spiral inductor modeling.All elements used in the two topologies for accurately predicting the characteristics of spiral inductors at radio frequencies are constructed in geometry-dependent equations for scalable modeling.Then a comparison between the 1-πand 2-πscalable models is made from the following aspects：the complexity of equivalent circuit models and parameter-extraction procedures,scalable rules and the accuracy of scalable models.The two scalable models are further verified by the excellent match between the measured and simulated results on extracted parameters up to self-resonant frequency（SRF） for a set of spiral inductors with different L,R and N,which are fabricated by employing 0.18-μm 1P6M RF CMOS technology.