Effect of Pulse and dc Formation on the Performance of One-Transistor and One-Resistor Resistance Random Access Memory Devices

We investigate the effect of the formation process under pulse and dc modes on the performance of one transistor and one resistor （1 T1R） resistance random access memory （RRAM） device. All the devices are operated under the same test conditions, except for the initial formation process with different modes. Based on the statistical results, the high resistance state （FIRS） under the dc forming mode shows a lower value with better distribution compared with that under the pulse mode. One of the possible reasons for such a phenomenon originates from different properties of conductive filament （CF） formed in the resistive switching layer under two different modes. For the dc forming mode, the formed filament is thought to be continuous, which is hard to be ruptured, resulting in a lower HRS. However, in the case of pulse forming, the filament is discontinuous where the transport mechanism is governed by hopping. The low resistance state （LRS） can be easily changed by removing a few trapping states from the conducting path. Hence, a higher FIRS is thus observed. However, the HRS resistance is highly dependent on the length of the gap opened. A slight variation of the gap length will cause wide dispersion of resistance.

Lightweight and highly robust memristor-based hybrid neural networks for electroencephalogram signal processing

Memristor-based neuromorphic computing shows great potential for high-speed and high-throughput signal processing applications,such as electroencephalogram(EEG)signal processing.Nonetheless,the size of one-transistor one-resistor(1T1R)memristor arrays is limited by the non-ideality of the devices,which prevents the hardware implementation of large and complex networks.In this work,we propose the depthwise separable convolution and bidirectional gate recurrent unit(DSC-BiGRU)network,a lightweight and highly robust hybrid neural network based on 1T1R arrays that enables efficient processing of EEG signals in the temporal,frequency and spatial domains by hybridizing DSC and BiGRU blocks.The network size is reduced and the network robustness is improved while ensuring the network classification accuracy.In the simulation,the measured non-idealities of the 1T1R array are brought into the network through statistical analysis.Compared with traditional convolutional networks,the network parameters are reduced by 95%and the network classification accuracy is improved by 21%at a 95%array yield rate and 5%tolerable error.This work demonstrates that lightweight and highly robust networks based on memristor arrays hold great promise for applications that rely on low consumption and high efficiency.

The Bipolar Field-Effect Transistor:XⅢ. Physical Realizations of the Transistor and Circuits(One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

This paper reports the physical realization of the Bipolar Field-Effect Transistor （BiFET） and its onetransistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor （the bulk transistor） and the impurethin-base Silicon-on-Insulator （SOI） transistor and the two-MOS-gates on thin base transistors （the FinFET and the Thin Film Transistor TFF）. Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.