Design of 32 kbit one-time programmable memory for microcontroller units

A 32 kbit OTP(one-time programmable)memory for MCUs(micro-controller units)used in remote controllers was designed.This OTP memory is used for program and data storage.It is required to apply 5.5V to BL(bit-line)and 11V to WL(word-line)for a OTP cell of 0.35μm ETOX(EEPROM tunnel oxide)type by MagnaChip.We use 5V transistors on column data paths to reduce the area of column data paths since they require small areas.In addition,we secure device reliability by using HV(high-voltage)transistors in the WL driver.Furthermore,we change from a static logic to a dynamic logic used for the WL driver in the core circuit.Also,we optimize the WD(write data)switch circuit.Thus,we can implement them with a small-area design.In addition,we implement the address predecoder with a small-area logic circuit.The area of the designed 32 kbit OTP with 5V and HV devices is 674.725μm×258.75μm(=0.1745mm2)and is 56.3% smaller than that using 3.3V devices.

A novel one-time-programmable memory unit based on Schottky-type p-GaN diode

In this work,a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed.During the programming process,the junction switches from a high-resistance state to a low-resistance state through Schottky junction breakdown,and the state is permanently preserved.The memory unit features a current ratio of more than 10^(3),a read voltage window of 6 V,a programming time of less than 10^(−4)s,a stability of more than 108 read cycles,and a lifetime of far more than 10 years.Besides,the fabrication of the device is fully compatible with commercial Si-based GaN process platforms,which is of great significance for the realization of low-cost read-only memory in all-GaN integration.

Design of 1 kbit antifuse one time programmable memory IP using dual program voltage

A 1 kbit antifuse one time programmable(OTP) memory IP,which is one of the non-volatile memory IPs,was designed and used for power management integrated circuits(ICs).A conventional antifuse OTP cell using a single positive program voltage(VPP) has a problem when applying a higher voltage than the breakdown voltage of the thin gate oxides and at the same time,securing the reliability of medium voltage(VM) devices that are thick gate transistors.A new antifuse OTP cell using a dual program voltage was proposed to prevent the possibility for failures in a qualification test or the yield drop.For the newly proposed cell,a stable sensing is secured from the post-program resistances of several ten thousand ohms or below due to the voltage higher than the hard breakdown voltage applied to the terminals of the antifuse.The layout size of the designed 1 kbit antifuse OTP memory IP with Dongbu HiTek's 0.18 μm Bipolar-CMOS-DMOS(BCD) process is 567.9 μm×205.135 μm and the post-program resistance of an antifuse is predicted to be several ten thousand ohms.

一次性可编程存储器的数据保持特性建模及分析

基于300 mm 0.18μm MS 5 V工艺平台设计并流片了1k×16一次性可编程OTP器件,并对存储单元的结构、工作原理及工艺等可能影响数据保持寿命的因素进行了分析。根据Arrhenius寿命模型对不同样品设置了高温老化实验测试,收集数据并对OTP器件的保持特性进行建模。通过225℃、250℃和275℃条件下的高温老化加速实验,拟合样品最大数据保持时间曲线。在生产过程中可能出现的最差产品条件下,对1/(kT)与数据保持时间曲线进行数学拟合,计算在不同失效条件下的浮栅电荷泄漏的激活能和最大数据保持时间。

大规模芯片内嵌存储器的BIST测试方法研究

随着大规模芯片的块存储器(block random access memory,BRAM)数量不断增多,常见的存储器内建自测试(memory build-in-self test,Mbist)方法存在故障覆盖率低、灵活性差等问题。为此,提出了一种新的基于可编程有限状态机的Mbist方法,通过3个计数器驱动的可编程Mbist控制模块和算法模块集成8种测试算法,提高故障覆盖率和灵活性。采用Verilog语言设计了所提出的Mbist电路,通过Modelsim对1 Kbit×36的BRAM进行仿真并在自动化测试系统上进行了实际测试。实验结果表明,该方法对BRAM进行测试能够准确定位故障位置,故障的检测率提高了15.625%,测试效率提高了26.1%,灵活性差的问题也得到了很大改善。

Design of 32-bit differential paired eFuse OTP memory in a form of two-dimensional array

A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was proposed.The sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference voltage.With this 2D array of differential paired eFuse OTP memory cells,we design a 32-bit eFuse OTP memory IP.We use a sense amplifier based D F/F circuit as the BL(bit-line)SA(sense amplifier)and design a sensing margin test circuit with a variable pull-up load.It is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.

世界记忆项目的价值旨趣、空间向度与中国话语——兼评《传承人类记忆遗产——联合国教科文组织世界记忆项目研究》

《传承人类记忆遗产——联合国教科文组织世界记忆项目研究》是国内首部全面介绍世界记忆项目的教科书级著作。世界记忆项目的逻辑性、理念性与导向性,承载力、形塑力与建构力,以及中国作为参与者、支持者与领导者的独特视角和经验值得重点关注。

基于LSTM-DT模型的低碳工业互联网网络安全态势平台

低碳工业互联网网络安全态势平台的网络拓扑结构具有一定的限制性,导致节点之间的通信受到约束,使得平台吞吐量较小,无法满足相应的吞吐量需求。为此,提出基于长短时记忆-决策树(Long Short-Term Memory-DecisionTree,LSTM-DT)模型的低碳工业互联网网络安全态势平台设计研究。将GF-PR6K可编程控制面板作为硬件装置;利用长短期记忆网络,在记忆当前时刻低碳工业互联网网络状态信息的基础上,在下一时刻有选择地传递或遗忘低碳工业互联网网络的隐藏状态,最大限度降低低碳工业互联网网络安全态势分析阶段的冗余计算量,利用DT对低碳工业互联网网络状态序列信息进行综合。在测试结果中,设计平台吞吐量不仅呈现出了随着测试互联网网络构成及规模的增加逐渐增大的特点,且对应的涨幅明显,当节点之间通信距离由15 m增加至50 m时,对应的吞吐量增幅仅为1.00 kb。

Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 ~tm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm ×100.15μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.

Design of 256 bit single-poly MTP memory based on BCD process

We propose a single-poly MTP （multi-time programmable） cell consisting of one capacitor and two transistors based on MagnaChip＇s BCD process. The area of a unit cell is 37.743 75μm^2. The proposed single-poly MTP cell is erased and programmed by the FN tunnelling scheme. We design a 256 bit MTP memory for PMICs （power management ICs） using the proposed single-poly MTP cells. For small-area designs, we propose a selection circuit between V10V and VSV, and a WL （word-line） driver by simplifying its logic circuit. We reduce the total layout area by using pumped internal node voltages from a seven-stage cross-coupled charge pump for V10V （=10 V） and V5V （=5 V） without any additional charge pumps. The layout size of the designed 256 bit MTP memory is 618.250 μm × 437.425μm.

保存数字时代的人类遗产——联合国教科文组织数字遗产政策演变与展望

数字技术发展改变了遗产的生成形态与保护途径,催生了“数字遗产”。然而,数字载体更替、数字技术迭代等加速数字信息的消亡,使其面临长期保存危机。文章梳理联合国教科文组织《保存数字遗产宪章》颁布以来,近20年数字遗产保护政策演变,探讨其核心要义,分析其发展趋势,为数字环境中的信息长期保存及文化遗产元素的挖掘提供借鉴。

基于可编辑颜色和形状记忆液晶网络的信息存储材料

近年来,液晶网络材料因为在人工肌肉、软体机器人、微流控制器和4D打印材料等智能软器件领域的应用受到了越来越多的关注。液晶网络材料在化学结构上同时包含聚合物交联网络和液晶基元,在性能上同时具有聚合物的可加工性、化学稳定性和力学特性以及液晶可调的各向异性,因此具有外观易编辑、功能可调、对多种刺激都能响应等优点。利用这些特点,可以将指定的形状或颜色信息精确地写入到材料中,同时在特定外界刺激(光,热,电场,溶剂等)下使信息再次显现,实现信息的存储、加密与读取。本文简要论述了具有可编辑颜色(包括结构色和荧光颜色)和形状记忆的液晶网络材料的信息存储方式,重点介绍了液晶网络材料在伪装、多级信息存储与信息传递等方面的应用研究进展。

形状记忆合金复合纱线及其面料驱动性能

为研究开发高性能纺织基人工肌肉,设计并制备了以镍钛合金为芯丝、聚酰亚胺纤维为外包纤维的热驱动复合纱线致动器。利用该复合包芯纱成功制备了一种形状可编程的机织物致动器,并初步探索了复合纱线及其织物的力学性能和热驱动特性。研究结果表明:复合纱线及其织物受热驱动后将恢复到初始线性状态,加载的温度越高,形状记忆复合纱线的模量越大,回复应力也越大;该纱线具有良好的电加热和热稳定性能,加载的电流和电压越大,纱线温度越高,达到稳定态的时间越短;纱线在5 V电压下能在6.2 s内完成驱动。该复合织物致动器具有耐高温、形状可编程的特性,可实现不同模式的驱动。

基于JESD204B协议的智能信号处理SoC中自适应缓冲结构

JESD204B(简称204B)是智能信号处理系统级芯片(SoC)中连接高速模数/数模(AD/DA)转换的重要接口,将SoC系统结构与204B标准要求进行集成设计时,自适应缓冲结构(ABS)可弥补204B协议对数据传输缺乏流量控制的缺陷,并通过设置自适应缓冲与流控机制,保证数据传输的可靠性。经过现场可编程门阵列(FPGA)验证,SoC在204B接口可以达到4×12.5 Gbit/s的数据传输带宽,证明设计的204B接口方案在智能信号处理SoC中的可行性和有效性,满足智能信号处理SoC对于数据接口的要求。该设计方案的实现对无流量控制数据传输协议与SoC体系结构的集成有借鉴意义。

基于FPGA的TCAM实现方法综述

近年来,FPGA由于其可编程和高性能的特性在高速网络中被大量使用,而在包处理中被广泛用于数据包分类等应用中的TCAM并没有内置于FPGA中。因此如何使用FPGA中的逻辑资源和存储资源来构建TCAM成为了研究热点。本文对主流的基于FPGA的TCAM实现方案进行了介绍和比较,包括基于块存储器(BRAM)的方案,基于分布式存储器(DRAM)的方案和基于触发器的方案。最后,对这些方案各自的优缺点和适用场景进行了总结。

基于时间递归神经网络的轨道车辆自检系统设计

针对轨道车辆内部复杂的信号和多样化的故障类型,为提高故障自检的快速性和有效性,设计了一种基于时间递归神经网络的轨道车辆自检系统,此系统中包含了基于FPGA的神经网络加速器、信号处理芯片、通信模块和传感器。加速器是利用时间递归神经网络LSTM作为自检系统内部智能化神经网络模型,采用剪枝、量化和编码等方式对模型进行了轻量化压缩,最后设计相应的加速器部署在自检系统中,同时完成了LSTM网络轻量化压缩实验和神经网络加速器实验。实验结果表明,自检系统的神经网络压缩算法的设计虽然使模型准确率下降了12.1%,但是压缩率可达7.1%;加速器部分在FPGA部署时仅占用了1.28%的硬件存储资源,性能则可以达到200 MHz,吞吐率为19.39 GOPS。

Recent advances in multifunctional shape memory photonic crystals and practical applications

Shape memory photonic crystals(SMPCs)are smart composite materials with changeable structural color integrated by shape memory polymer and photonic crystals.SMPC can produce one or more temporary shapes through nanoscale deformation,memorizing current states.SMPC can be recovered to their original shapes or some intermediate states under external stimuli,accompanied by the variation of structural color.As porous carriers with built-in sensing properties,SMPCs promoted the interdisciplinary development of nanophotonic technology in materials science,environmental engineering,biomedicine,chemical engineering,and mechanics.Herein,the recent progress on multifunctional SMPCs and practical applications,including traditional and cold programmable SMPCs,is summarized and discussed.The primary concern is shape programming at the nanoscale that has demonstrated numerous attractive functions,including smart sensing,ink-free printing,solvent detection,reprogrammable gradient wetting,and controllable bubble transportation,under variations of the surface nanostructure.It aims to figure out the nanoscale shape memory effects on structural color conversion and additional performance,inspiring the fabrication of the next generation of SMPCs.Finally,perspectives on future research directions and applications are also presented.It is believed that multifunctional SMPCs are powerful nanophotonic tools for the interdisciplinary development of numerous disciplines in the future.

基于NVMe的超高速多通道遥感相机模拟源设备研制

针对当前遥感卫星电荷耦合器件(CCD)相机幅宽越来越大,速率越来越高,现有相机模拟源设备数据输出带宽不足的问题,提出并实现了一种基于非易失性存储器Express(NVMe)的超高速多通道遥感相机模拟源设备。该设备利用现场可编程逻辑门阵列(FPGA)实现4组NVMe SSD主机控制器,完成对固态硬盘(SSD)的读写操作;同时利用DMA控制器读取DDR4中缓存数据,数据经封装处理后通过光纤接口输出。实验结果表明:NVMe主机控制器的写平均速率可以达到1.7 GBps,读平均速率达到3.2 GBps。模拟源系统整体存储容量8 TB,对外输出带宽高达80 Gbps,支持8路光纤接口输出。该模拟源具有较强的稳定性及良好的可扩展性,已成功应用在某遥感卫星CCD相机模拟源系统中,为数传等设备的测试以及调试提供了充分保障。

SRAM型FPGA单粒子辐照试验系统技术研究

单粒子辐射效应严重制约FPGA的空间应用,为提高FPGA在辐射环境中的可靠性,深入研究抗辐射加固FPGA单粒子效应评估方法,设计优化单粒子效应评估方案,开发相应的评估系统,提出基于SRAM时序修正的码流存储比较技术和基于SelectMAP端口配置回读技术。借助国内高能量大注量率的辐照试验环境,完成FPGA单粒子翻转(SEU)、单粒子闩锁(SEL)和单粒子功能中断(SEFI)等单粒子效应的检测,试验结果表明,该方法可以科学有效地对SRAM型FPGA抗单粒子辐射性能进行评估。

高速大容量多通道数据采集系统设计

根据某型号通信实验系统中数据采集单元的设计要求 ,提出了一种高速、大容量、多通道数据采集系统的设计方案。该方案以同步动态存储器 ( Synchronous dynamic random access memory,SDRAM)组成的计算机内存条为存储介质 ,以现场可编程门阵列 ( Field programmable gate array,FPGA)为数字逻辑控制的核心 ,并通过硬件描述语言 ( VHSIC hardware description language,VHDL)编程实现了控制 SDRAM所需的接口电路 ,从而使硬件电路软件化 ,降低了硬件成本。本文重点介绍了该采集系统的硬件设计原理和软件设计框架。