Single Event Transients of Operational Amplifier and Optocoupler

The single event transient effects of the operational amplifier LM124J and the optocoupler HCPL 5231 are investigated by a pulsed laser test facility. The relation of transient pulse shape to pulsed laser equivalent LET is tested,the sensitive areas of the SET effects are identified in voltage follower application mode of LM124J, and the mechanism is initially analyzed. The transient amplitude and duration of HCPL5231 at various equivalent LET are examined,and the SET cross-section is measured. The results of our test and heavy ion experimental data coincide closely,indicating that a pulsed laser test facility is a valid tool for single event effect evaluation.

Active Damping of Milling Vibration Using Operational Amplifier Circuit

The problem of chatter vibration is associated with adverse consequences that often lead to tool impairment and poor surface finished in a workpiece, and thus, controlling or suppressing chatter vibrations is of great significance to improve machining quality. In this paper, a workpiece and an actuator dynamics are considered in modeling and controller design. A proportional-integral controller(PI) is presented to control and actively damp the chatter vibration of a workpiece in the milling process. The controller is chosen on the basis of its highly stable output and a smaller amount of steady-state error. The controller is realized using analog operational amplifier circuit. The work has contributed to planning a novel approach that addresses the problem of chatter vibration in spite of technical hitches in modeling and controller design. The method can also lead to considerable reduction in vibrations and can be beneficial in industries in term of cost reduction and energy saving. The application of this method is verified using active damping device actuator(ADD) in the milling of steel.

A Three-Stage Operational Amplifier for a Wide Range of Capacitive Loads

This paper presents a three-stage CMOS operational amplifier （opamp） that combines accuracy with stability for a wide range of capacitive loads. A so-called quenching capacitor is added to a multipath nested Miller compensation （MNMC） topology to obtain stability for a wide range of capacitive loads. Theoretical analysis and mathematical formulas are provided to prove the improvement in stability. A prototype of this frequency compen- sation scheme is implemented in a 0.7μm CMOS process. Measurement′s show that the amplifier can drive capaci- tive loads ranging from 100pF to 100/μF with a gain of 90dB and a minimum phase margin of 26°. The amplifier has a unity-gain bandwidth of 1MHz for a 100pF capacitive load. It employs a quenching capacitance of 18pF.

Low-Power Operational Amplifier for Real-Time Signal Processing System of Micro Air Vehicle

A low-power complementary metal oxide semiconductor（CMOS） operational amplifier （op-amp） for real-time signal processing of micro air vehicle （MAV） is designed in this paper.Traditional folded cascode architecture with positive channel metal oxide semiconductor（PMOS） differential input transistors and sub-threshold technology are applied under the low supply voltage.Simulation results show that this amplifier has significantly low power,while maintaining almost the same gain,bandwidth and other key performances.The power required is only 0.12 mW,which is applicable to low-power and low-voltage real-time signal acquisition and processing system.

Symbolic Macromodeling for Statistical Simulation of Operational Amplifiers

Symbolic circuit simulator is traditionally applied to the small-signal analysis of analog circuits. This paper establishes a symbolic behavioral macromodeling method applicable to both small-signal and large-signal analysis of general two-stage operational amplifiers （op-amps）. The proposed method creates a two-pole parametric macromodel whose parameters are analytical functions of the circuit element parameters generated by a symbolic circuit simulator. A moment matching technique is used in deriving the analytical model parameter. The created parametric behavioral model can be used for op-amps performance simulation in both frequency and time domains. In particular, the parametric models are highly suited for fast statistical simulation of op-amps in the time-domain. Experiment results show that the statistical distributions of the op-amp slew and settling time characterized by the proposed model agree well with the transistor-level results in addition to achieving significant speedup.

Impact of TID on response to pulsed X-ray irradiation in the bipolar operational amplifier

Groups of a typical operational amplifier-μA741 were irradiated in a cobalt unit, each group accumulating a different total ionizing dose （TID）. The results showed that the TID caused power consumption current and slew rate （SR） to degenerate in ultra-linearity, owing to a severe reduction in the current gain of the internal LPNP transistors. Pulsed X-ray irradiation experiments were carried out on the μA741 groups with different values, and the results revealed that the impact on the response to the pulsed X-ray irradiation was greater when the devices absorbed more TID. The mechanism for this is explained on the basis of the circuit construction of the μA741; the sensitive parameters of the circuit were obtained via simulation on SP1CE. The simulation results additionally showed that if the sensitive parameters were optimized, the duration of interruption caused by the pulsed X-ray irradiation would be reduced significantly. In addition, several proposals are provided for hardening the devices.

A constant-g_m and high-slew-rate operational amplifier for an LCD driver

To drive the backplane of a liquid crystal display device and achieve different kinds of grey levels, a high-slew-rate operational amplifier with constant-gin input stage is presented. A Zener-diode structure is inserted between the tails of the complementary input pairs to keep the grn of the input stage constant. A novel slew rate enhancement circuit is implemented to achieve a very high slew rate. The chip has been implemented in a 0.5μm CMOS process and the chip area of the operational amplifier circuit is 0.11 mm^2. The testing results indicate that in the 5-8 V input range, the maximum gm fluctuation is only 4.2%. The result exhibits a high slew rate of 111 V/μs and 102 V/μs for the rising and falling edges under a 20 pF capacitance load, and the low frequency gain is up to 109 dB with a phase margin of 70 ℃.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper,capable of operating with minimum supply voltage at1 V.A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current,which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier.A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted,which not only improves the sense window enhancing read precision but also saves power consumption.The sense amplifier was implemented in a flash realized in 90 run flash technology.Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125℃.

A 12-bit,40-Ms/s pipelined ADC with an improved operational amplifier

This paper proposes a 12-bit,40-Ms/s pipelined analog-to-digital converter（ADC） with an improved high-gain and wide-bandwidth operational amplifier（opamp）.Based on the architecture of the proposed ADC,the non-ideal factors of opamps are first analyzed,which have the significant impact on the ADC＇s resolution.Then,the compensation techniques of the ADC＇s opamp are presented to restrain the negative effect introduced by the gainboosting technique and switched-capacitor common-mode-feedback structure.After analysis and optimization,the ADC implemented in a 0.35μm standard CMOS process shows a maximum signal-to-noise distortion ratio of 60.5 dB and a spurious-free dynamic range of 74.5 dB,respectively,at a 40 MHz sample clock with over 2 Vpp input range.

Design of a high-performance PJFET for the input stage of an integrated operational amplifier

With Shockley＇s approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier （OPA） was realized. The high-performance PJFET device was developed in the Bi-FET process technology. The measured specifications are as follows. The top-gate junction depth is about 0.1 μm, the gate-leakage current is less than 5 pA, the breakdown voltage is more than 80 V, and the pinch-off voltage is optional between 0.8 and 2.0 V. The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA. The measured results show that the OPA has a bias current of less than 50 pA, voltage noise of less than 50 nV/Hz^1/2, and current noise of less than 0.05 pA/Hz^1/2.

Design procedure for optimizing CMOS low noise operational amplifiers

This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier. The design procedure focuses on the noise performance, which is the key requirement for low noise operational amplifiers. Based on the noise level and other specifications such as bandwidth, signal swing, slew rate, and power consumption, the device sizes and the biasing conditions are derived. In order to verify the proposed design procedure, a three-stage operational amplifier has been designed. The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.

Annealing behavior of radiation damage in JFET-input operational amplifiers

The elevated and room temperature annealing behavior of radiation damage in JFET-input operational amplifiers （op-amps） were investigated. High- and low-dose-rate irradiation results show that one of the JFET-input op-amps studied in this paper exhibits enhanced low-dose-rate sensitivity and the other shows time-dependent effect. The offset voltage of both op-amps increases during long-term annealing at room temperature. However, the offset voltage decreases at elevated temperature. The dramatic difference in annealing behavior at room and elevated temperatures indicates the migration behavior of radiation-induced species at elevated and room temperatures. This provides useful information to understand the degradation and annealing mechanisms in JFET-input op-amps under total ionizing radiation. Moreover, the annealing of oxide trapped charges should be taken into consideration, when using elevated temperature methods to evaluate low-dose-rate damage.

A novel low-voltage operational amplifier for low-power pipelined ADCs

A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.

Proton radiation effect of NPN-input operational amplifier under different bias conditions

NPN-input bipolar operational amplifiers LM741 were irradiated with ^60Coγ-ray, 3 MeV protons and10 MeV protons respectively at different biases to investigating the proton radiation response of the NPN-input operational amplifier. The comparison of protons with^60Coγ-rays showed that the proton radiation mainly induced ionization damage in LM741. Under different bias conditions, the radiation sensitivity is different; zero biased devices show more radiation sensitivity in the input biased current than forward biased devices. Supply current（±Icc）is another parameter that is sensitive to proton radiation,^60Coγ-ray, 3 MeV and 10 MeV proton irradiation would induce a different irradiation response in ±Icc, which is caused by different ionization energy deposition and displacement energy deposition of^60Coγ-ray, 3 MeV and 10 MeV proton irradiation.

A low-powerlow-voltage slew-rate enhancement circuit for two-stage operational amplifiers

A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers. The enhancer utilizes the class-AB input stage to improve current efficiency, while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier. During the slewing period, the enhancer detects input differential voltage of the amplifier, and produces external enhancement currents for the amplifier, driving load capacitors to charge/discharge faster. Simulation results show that, fora large input step, the enhancerreduces settling time by nearly 50%. When the circuit is employed in a sample-and-hold circuit, it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB. The proposed circuit is very suitable to operate under a low voltage （1.2 V or below） with a standby current of 200 μA.

Dual-Mode Low Power Pipelined ADC with Pre-charged Switched Operational Amplifier

This paper describes a 12-bit 40-MS/s and 8-bit 80-MS/s dual-mode low power pipelined analog-to-digital converter （ADC）. An improved multiplying digital-to-analog converter is used to provide the dual-mode operation. A pre-charged fast power-on switched operational amplifier is used to reduce the power consumption of the pipelined ADC to 28.98 mW/32.74 mW at 40 MHz/80 MHz sampling rates. The ADC was designed in a 1.8-V 1P6M 0.18-μm CMOS process. Simulations indicate that the ADC exhibits a spurious free dynamic range of 90.24 dB/58.33 dB and signal-to-noise-and-distortion ratio of 73.81 dB/47.85 dB at 40 MHz/80 MHz sampling frequencies for a 19-MHz input sinusoidal signal.

Optimization Design of Two-Stage Operational Amplifier with Frequency Compensation via Geometric Programming

An optimization design technique to obtain global solution for a two-stage operational amplifier(op-amp) with frequency compensation is presented.This frequency compensation technique can adjust the equivalent resistance to guarantee that the phase margin is stable even though circumstance temperature varies.Geometric programming is used to optimize the component values and transistor dimensions.It is used in this analog integrated circuit design to calculate these parameters automatically.This globally optimal amplifier obtains minimum power while other specifications are fulfilled.

Efficient Slew-Rate Enhanced Operational Transconductance Amplifier

Today, along with the prevalent use of portable equipment, wireless, and other battery powered systems, the demand for amplifiers with a high gain-bandwidth product（GBW）, slew rate（SR）, and at the same time very low static power dissipation is growing. In this work, an operational transconductance amplifier（OTA） with an enhanced SR is proposed. By inserting a sensing resistor in the input port of the current mirror in the OTA, the voltage drop across the resistor is converted into an output current containing a term in proportion to the square of the voltage, and then the SR of the proposed OTA is significantly enhanced and the current dissipation can be reduced. The proposed OTA is designed and simulated with a 0.5μm complementary metal oxide semiconductor（CMOS） process. The simulation results show that the SR is 4.54V/μs, increased by 8.25 times than that of the conventional design, while the current dissipation is only 87.3%.

Optimization and design of inter-stage amplifier with wide output swing,high speed and high accuracy

To satisfy the design requirements of analog-to-digital converter （ADC） of high speed sampling system in an infrared focal plane array tester with 1024 × 1024 pixels, a first inter-stage amplifier of 12-bit 40- Msample/s pipelined ADC was designed with 0. 35 μm CMOS technology. On the basis of traditional two-stage amplifier, the cross-coupled class AB output stage and cascode compensation were adopted to improve the output vohage swing and bandwidth. Power dissipation was optimized with math tools. Circuit and layout design were completed. Simulation results show that the designed amplifier has good performance of 95 dB dc gain, ±2 V output voltage swing, 190 MHz bandwidth and 63° phase margin with feedback factor 1/4, 33 mW power dissipation and so on, which can meet the system requirements.

Design of an OP-AMP Based on a LDO Regulator

An operational amplifier （OP-AMP） with a ground current of about 0.6μA is presented. Moreover, this amplifier reaps the benefits of incorporating a foldback current limiting circuit,which enables the low-dropout voltage regulator without the need of a special current limiting subblock. Therefore,the object of ultra-low power is realized because of a great reduction in transistors and current limbs.