Light-triggered two-dimensional lateral homogeneous p-n diodes for opto-electrical interconnection circuits

The realization of light-triggered devices where light is used as external stimulus to control the device performances is a long-standing goal in modern opto-electrical interconnection circuits.In this work,it reveals that light illumination can induce the formation of p-n junctions along two-dimensional conduction channels.The results indicate that the dominant charge carrier type and density in black phosphorus(BP)conduction channel can be effectively modulated by the underlying cadmium sulfide(CdS)photogate layer under light illumination.This enables flexible switching of the working state between BP resistor and BP p-n diode in the designed semi-photo-gate transistor(SPGT)devices when switching the light on and off(ultra-low threshold light power).Simultaneously,the achieved BP p-n junctions also exhibit ultra-high photoresponsivity and evident photovoltaic properties.That is to say,light can be employed as external stimulus to define the BP p-n junctions,and in turn the p-n junctions will further convert the light into electrical power,showing all-in-one opto-electrical interconnection properties.Moreover,the SPGT device architecture is also applicable for construction of other ambipolar semiconductor-based(WSe2-and MoTe2-based)p-n diodes.Such universal all-in-one light-triggered lateral homogeneous pn junctions with ultra-low energy consumption should open a new pathway toward novel optoelectronic devices and deliver various new applications.

BALANCED TRUNCATED MODELS OF C INTERCONNECT CIRCUITS AND THEIR SIMULATION

The Balanced Truncation Method (BTM) is applied to an even distributed RC interconnect case by using Wang's closed-forms of even distributed RC interconnect models. The results show that extremely high order RC interconnect can be high-accurately approximated by only third order balanced model. Related simulations are executed in both time domain and frequency domain. The results may be applied to VLSI interconnect model reduction and design.

ANALYSIS OF THE TRANSMISSION PROPERTIES OF TAPERED MUTLICONDUCTOR INTERCONNECTING BUSES IN HIGH-SPEED INTEGRATED CIRCUITS

Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach, a tapered bus system can be analyzed as a set of cascaded uniform buses with slightly different strip widths. Obtained results are in good agreement with the experimental data.

Unraveling complexity of interconnected regulatory circuits in lipid metabolism

In this issue of Journal of Biomedical Research,3review articles are published that cover a broad range of topics addressing current understanding on regulation of nutrient metabolism through protein phosphatases,homeostatic regulation of cellular lipid droplets by small GTPases,and mechanisms by which hepatic assembly and secretion of triglyceride-rich lipoproteins are regulated.

TRANSIENT ANALYSIS OF TRANSMISSION LINE CIRCUITS BASED ON THE SEMIDISCRETIZATION OF TELEGRAPH EQUATIONS

A new transient analysis method for the transmission line circuits is presented in this paper. Based on the semidiscretization of the telegraph equations, a discretized time domain companion models for the transmission lines which can be conveniently implemented in a general circuit simulator such as SPICE is derived. The computation required for the model is linear with time, equivalent to the recursive convolution-based method. The formulations for both single and coupled lossy transmission lines are given. Numerical experiments are carried out to demonstrate the validity of the method.

Review of the Global Trend of Interconnect Reliability for Integrated Circuit

Interconnect reliability has been regarded as a discipline that must be seriously taken into account from the early design phase of integrated circuit (IC). In order to study the status and trend of the interconnect reliability, a comprehensive review of the published literatures is carried out. This can depict the global trend of ICs’ interconnect reliability and help the new entrants to understand the present situation of this area.

The Detection of Inter-Turn Short Circuits in the Stator Windings of Sensorless Operating Induction Motors

This work proposes an alternative strategy to the use of a speed sensor in the implementation of active and reactive power based model reference adaptive system (PQ-MRAS) estimator in order to calculate the rotor and stator resistances of an induction motor (IM) and the use of these parameters for the detection of inter-turn short circuits (ITSC) faults in the stator of this motor. The rotor and stator resistance estimation part of the IM is performed by the PQ-MRAS method in which the rotor angular velocity is reconstructed from the interconnected high gain observer (IHGO). The ITSC fault detection part is done by the derivation of stator resistance estimated by the PQ-MRAS estimator. In addition to the speed sensorless detection of ITSC faults of the IM, an approach to determine the number of shorted turns based on the difference between the phase current of the healthy and faulty machine is proposed. Simulation results obtained from the MATLAB/Simulink platform have shown that the PQ-MRAS estimator using an interconnected high-gain observer gives very similar results to those using the speed sensor. The estimation errors in the cases of speed variation and load torque are almost identical. Variations in stator and rotor resistances influence the performance of the observer and lead to poor estimation of the rotor resistance. The results of ITSC fault detection using IHGO are very similar to the results in the literature using the same diagnostic approach with a speed sensor.

Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection

A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.

An interconnect width and spacing optimization model considering scattering effect

As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has a serious impact on interconnection performance, such as delay and bandwidth. Based on the impact of the scattering effect on latency and bandwidth, this paper first presents the quality-factor model which optimises latency and bandwidth effectively with the consideration of the scattering effect. Then we obtain the analytical model of line width and spacing with application of curve-fitting method. The proposed model has been verified and compared based on the nano-scale CMOS technology. This optimisation model algorithm is simple and can be applied to the interconnection system optimal design of nano-scale integrated circuits.

Weighted Self-Adaptive Threshold Wavelets for Interpolation Point Selection Used in Interconnect MOR

As process technology development,model order reduction( MOR) has been regarded as a useful tool in analysis of on-chip interconnects. We propose a weighted self-adaptive threshold wavelet interpolation MOR method on account of Krylov subspace techniques. The interpolation points are selected by Haar wavelet using weighted self-adaptive threshold methods dynamically. Through the analyses of different types of circuits in very large scale integration( VLSI),the results show that the method proposed in this paper can be more accurate and efficient than Krylov subspace method of multi-shift expansion point using Haar wavelet that are no weighted self-adaptive threshold application in interest frequency range,and more accurate than Krylov subspace method of multi-shift expansion point based on the uniform interpolation point.

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-am and 90-nm complementary metal-oxide semiconductor （CMOS） interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.

Current sustainability and electromigration of Pd,Sc and Y thin-films as potential interconnects

The progress on novel interconnects for carbon nanotube(CNT)-based electronic circuit is by far behind the remarkable development of CNT-field effect transistors.The Cu interconnect material used in current integrated circuits seems not applicable for the novel interconnects,as it requires electrochemical deposition followed by chemical-mechanical polishing.We report our experimental results on the failure current density,resistivity,electromigration effect and failure mechanism of patterned stripes of Pd,Sc and Y thin-films,regarding them as the potential novel interconnects.The Pd stripes have a failure current density of(8~10)×106 A/cm^2(MA/cm^2),and they are stable when the working current density is as much as 90% of the failure current density.However,they show a resistivity around 210 μΩ·cm,which is 20 times of the bulk value and leaving room for improvement.Compared to Pd,the Sc stripes have a similar resistivity but smaller failure current density of 4~5 MA/cm^2.Y stripes seem not suitable for interconnects by showing even lower failure current density than that of Sc and evidence of oxidation.For comparison,Au stripes of the same dimensions show a failure current density of 30 MA/cm^2 and a resistivity around 4 μΩ·cm,making them also a good material as novel interconnects.

高速数字化三维集成式CCD-CMOS图像传感器

为了解决CCD与CMOS工艺兼容性低、互连集成制作难度大,以及芯片间接口匹配和高性能兼备等问题,对CCD器件拓扑结构与像元、CMOS读出电路、三维异质互连集成及高密度引脚封装等技术进行研究,提出了一种1024×256阵列规模的集成式CCD-CMOS图像传感器。该器件实现了CCD信号的高精度数字化处理、高速输出及多芯粒的技术融合,填补了国内CCDCMOS三维集成技术空白。测试结果表明:集成CCD-CMOS器件的光响应和成像功能正常,双边成像效果良好,图像无黑条和坏列,互连连通率(99.9%)满足三维集成要求,实现了集成式探测器件的大满阱高灵敏度成像(满阱电子数达165.28ke^(-)、峰值量子效率达86.1%)、高精度数字化(12bit)和高速输出(行频率达100.85kHz),满足集成化、数字化、小型化的多光谱探测成像系统要求。

基于电流体动力喷射的多层柔性电路垂直互联结构打印技术研究

柔性可拉伸电子器件在可穿戴电子产品和软体机器人等领域应用广泛。为了实现高度集成,不同层之间的电子器件需要通过垂直互联来连接在一起,因此,实现稳定的垂直互联至关重要。提出了一种可以通过电流体动力喷射直接打印低熔点液态金属立柱的方法,可以实现柔性电路的垂直互联。通过控制打印参数,可以打印出不同高度的金属立柱,以制作出不同高度的垂直互联。为了检测垂直互联结构的稳定性和可靠性,将制作的具有垂直互联通道的电路分别进行拉伸、弯曲检测,检测表明在数百次的弯曲和拉伸循环下,该电路具有稳定的电阻响应。制作了一个基于多层结构的带LED灯的无线感应线圈,以展示电流体动力喷射打印用于垂直互联的能力。

飞行器智能蒙皮异质多层电路制造技术进展

智能蒙皮在飞行器承载结构蒙皮表面集成异质多功能电路系统,是实现未来变体飞行器“Fly-by-Feel”的使能技术。飞行器智能蒙皮涉及多功能分布式传感系统、共形天线、频率选择表面、防/除冰等功能模块,这提升了飞行器态势感知能力并促进其结构向轻量化发展,其技术关键在于复杂3D结构表面异质多层电路的成型制造。针对智能蒙皮多功能电路制造难题,本文对不同种类曲面功能单元制造中的难点进行详细分析,并对比阐述适用于不同类型结构的制造技术,包括共形打印、通孔互联、曲面贴装、薄膜制备等。最后总结和展望了智能蒙皮异质多层电路制造技术面临的挑战和潜在解决方案,为下一代飞行器智能蒙皮制造技术的突破提供有益的参考。

三维集成电子封装中TGV技术及其器件应用进展

在三维(3D)集成电路中,层间电路封装及其互联互通主要依赖于垂直通孔结构,这是其突破传统二维集成电路布局的核心与关键。近年来,玻璃通孔(TGV)技术由于具备低成本、高性能、易于加工和应用前景广阔等优点,日益引起了科研人员和电子厂商们的关注与重视。首先综述了TGV技术的性能优势、工艺特点、制备方法及关键技术。在此基础上,总结了TGV技术在三维集成无源器件(IPD)、集成天线封装、微机电系统(MEMS)封装以及多芯片模块封装等多个三维集成电子封装领域中的应用进展。基于此,进一步展望了TGV技术在未来三维集成电子封装中的发展方向与应用前景。

健那绿B平整剂对芯片互连钴的电沉积成核机理研究

目的探究了钴互连金属电子电镀工艺中的电镀成核机理,使用健那绿B(Janus Green B,JGB)对钴的电沉积进行进一步优化,并研究了JGB在改善电镀质量过程中的作用机理。方法采用电化学测试方法包括循环伏安、电流瞬态曲线,以及表征方法包括扫描电子显微镜(SEM)以及X射线衍射光谱(XRD),对钴在阻挡层Ti N上的电子电镀机理以及JGB作用下的成核特点及晶体特性等进行研究。结果测试得到了关于体系的电化学曲线以及薄膜微观表征图样,发现了JGB的成核特征,并在无金属阳离子的体系下进行对照实验,进而得出JGB对钴电沉积体系的影响机理。结论JGB促进了体系氢还原的进行,并改变了钴的成核特征,包括成核大小和数目,进而提升了电沉积质量,实现了更高的薄膜沉积覆盖率。JGB在体系中发生一系列电化学反应生成产物γ,产物γ由于带有不饱和N原子(显正电),会优先吸附到阴极的凸起处,γ分子剩余C—H—N结构可以抑制新的钴原子成核,从而增强电极表面还原沉积的平整度,使晶粒生长更加均匀。

面向数据中心的超高速光模块板级信号完整性研究

【目的】人工智能的高速发展对数据中心算力提出了更高的要求。光模块作为数据中心光/电互连的核心器件,其设计也将迎来巨大挑战。随着光模块速率的不断提升,信号完整性问题成为制约光模块性能不可忽视的瓶颈。因此为了设计出满足数据中心光互连,特别是高性能计算场景速率要求的超高速光模块,需要对光模块内部高速链路进行优化设计。【方法】文章以一款双密度4通道小型可插拔(QSFP-DD)光模块设计方案为例,对光模块中影响信号完整性的因素进行了仿真优化。具体工作为,从理论角度分析了链路上引起信号完整性问题的部分,如过孔和球栅阵列(BGA)焊球,并讨论了优化这些性能的改进方法。特别是分析了针对50 GHz以上频段信号传输的优化方法,使高速链路能实现超高速4阶电平脉冲幅度调制(PAM4)信号低损耗传输。另外,还研究了整体高速通道的传输性能,并利用4端口矢量网络分析仪进行了测试。【结果】研究结果表明,该设计方案能够达到所需的传输带宽并且能有效削弱谐振。全通道仿真结果显示所有通道传输带宽内回波损耗低于-15 dB,插入损耗低于3 dB,可实现224 Gbit/s PAM4信号低损耗传输,同时测试结果与仿真结果基本相符,证明文章所提设计方案能满足数据中心高速光互连对光模块速率的需求。【结论】文章所提光模块信号完整性设计方法对今后超高速光模块设计具有重要的指导意义,同时也可以为其他各类高速电路设计提供参考。

某型号导引头电子组件柔性互连技术研究

导引头系列产品中,非规则线缆的广泛应用、大批量需求及纯手工制作的生产特点,已满足不了导引头生产装配的自动化发展需求。针对导引头系列产品的小型化、轻量化、集成化发展趋势,需要一种新型电气互连方式来解决产品生产过程中非规则线缆制作这一瓶颈问题。利用电子组件柔性互连技术,采用刚柔结合印制板制造形式,实现了电信号在导引头内的稳定传输与可靠连接,经过抗载验证,满足了导引头抗载应用需求,达到了导引头非规则线缆自动化、批量化制作的目的。