Output Voltage Ripple (OVR) Reduction of Boost Converter Using Particle Swarm Optimization

KY Boost Converter, a modern invention in the field of non-isolated DC-DC boost converter is identified for minimum voltage ripple. KY boost converter is the com- bination of KY converter and traditional boost converter. Such a converter has con- tinuous input and output inductor current, different from the traditional boost con- verter. And hence this converter is very suitable for very low-ripple applications. The Particle Swarm Optimization (PSO) based controller, FUZZY based controller and open loop KY boost converter are designed in MATLAB/Simulink model. The simu- lated results show a reduction in output ripple from 1.18 V of the existing open loop KY boost converter output to 0.54 V in the FUZZY logic controlled converter out- put. Further reduction in output ripple to 0.29 V is achieved in the proposed PSO based converter. The simulated results also show the variation of switching pulses based on the different existing and proposed method.

Modeling and Analysis of Pulse Skip Modulation

The state space average model and the large signal models of Pulse Skip Modulation （PSM） mode are given in this paper. Farther more, based on these models and simulations of PSM converter circuits, the analysis of the characteristics of PSM converter is described in this paper, of which include efficiency, frequency spectrum analysis, output voltage ripple, response speed and interference rejection capability. Compared with PWM control mode, PSM converter has high efficiency, especially with fight loads, quick response, good interference rejection and good EMC characteristic. Improved PSM slightly, it could be a kind of good independent regulating mode during the whole operating process for a DC-DC converter. Finally, some experimental results are also presented in this paper.

Quantum state measurement in double quantum dots with a radio-frequency quantum point contact

We study the dynamics of two electron spins in coupled quantum dots （CQDs） monitored by a quantum point contact （QPC） detector. Their quantum state can be measured by embedding the QPC in an LC circuit. We derive the Bloch-type rate equations of the reduced density matrix for CQDs. Special attention is paid to the numerical results for the weak measurement condintion under a strong Coulomb interaction. It is shown that the evolution of QPC current always follows that of electron occupation in the right dot. In addition, we find that the output voltage of the circuit can reflect the evolution of QPC current when the circuit and QPC are approximately equal in frequency. In particular, the wave shape of the output voltage can be improved by adjusting the circuit resonance frequency and bandwidth.

A dual mode charge pump with adaptive output used in a class G audio power amplifier

A dual mode charge pump to produce an adaptive power supply for a class G audio power amplifier is presented.According to the amplitude of the input signals,the charge pump has two level output voltage rails available to save power.It operates both in current mode at high output load and in pulse frequency modulation （PFM） at light load to reduce the power dissipation.Also,dynamic adjustment of the power stage transistor size based on load current at the PFM mode is introduced to reduce the output voltage ripple and prevent the switching frequency from audio range.The prototype is implemented in 0.18μm 3.3 V CMOS technology.Experimental results show that the maximum power efficiency of the charge pump is 79.5%@ 0.5x mode and 83.6%@ lx mode.The output voltage ripple is less than 15 mV while providing 120 mA of the load current at PFM control and less than 18 mV while providing 300 mA of the load current at current mode control.An analytical model for ripple voltage and efficiency calculation of the proposed PFM control demonstrates reasonable agreement with measured results.

Long short-term memory deep learning model for predicting the dynamic performance of automotive PEMFC system

As a high efficiency hydrogen-to-power device,proton exchange membrane fuel cell(PEMFC)attracts much attention,especially for the automotive applications.Real-time prediction of output voltage and area specific resistance(ASR)via the on-board model is critical to monitor the health state of the automotive PEMFC stack.In this study,we use a transient PEMFC system model for dynamic process simulation of PEMFC to generate the dataset,and a long short-term memory(LSTM)deep learning model is developed to predict the dynamic per-formance of PEMFC.The results show that the developed LSTM deep learning model has much better perfor-mance than other models.A sensitivity analysis on the input features is performed,and three insensitive features are removed,that could slightly improve the prediction accuracy and significantly reduce the data volume.The neural structure,sequence duration,and sampling frequency are optimized.We find that the optimal sequence data duration for predicting ASR is 5 s or 20 s,and that for predicting output voltage is 40 s.The sampling frequency can be reduced from 10 Hz to 0.5 Hz and 0.25 Hz,which slightly affects the prediction accuracy,but obviously reduces the data volume and computation amount.

Research and design of a novel current mode charge pump

To meet the demands for a number of LEDs,a novel charge pump circuit with current mode control is proposed.Regulation is achieved by operating the current mirrors and the output current of the operational transconductance amplifier.In the steady state,the input current from power voltage retains constant,so reducing the noise induced on the input voltage source and improving the output voltage ripple.The charge pump small-signal model is used to describe the device’s dynamic behavior and stability.Analytical predictions were verified by Hspice simulation and testing.Load driving is up to 800 mA with a power voltage of 3.6 V,and the output voltage ripple is less than 45 mV.The output response time is less than 8μs,and the load current jumps from 400 to 800 mA.

Modeling and optimal design of LLC resonant converter using whale optimization algorithm

Resonant converter(RC)was brought under research in the 80’s widely,which can attain very small switching loss,therefore,facilitating resonant topologies to function at the high switching frequency.It is well addressed in the review that the optimal parameterization of the resonant converter is a crucial task.While the literature has come out with different methodologies,they are highly conceptual and so the uncertainty due to high theoretical impact persists.This paper intends to develop a Parameter Optimization(PO)algorithm for designing and developing of LLC-RC.The proposed algorithm overwhelms the limitation by introducing a nonconceptual model based on the simulated outcome.Specifically,the resonant current under start-up conditions is acquired from the literary outcome,and the intelligent model is constructed.Based on the proposed model,a renowned search algorithm called as Whale Optimization Algorithm(WOA)is exploited to optimize the time constant of the resonant converter,which is a critical design parameter.The objective model is derived as a function of start-up time and so the start-up time can be minimized.Moreover,the response speed of the output voltage is also increased.The proposed Whale Optimization Algorithm based Parameter Optimization(WOAPO)is compared with the conventional techniques such as IAPO,Ant Bee Colony-PO(ABC-PO),Particle Swarm Optimization-PO(PSOPO),FireFly PO(FFPO)and Grey Wolf Optimization(GWOPO).The obtained result verifies the performance of the proposed method in modeling LLC-RC system.

An 8 bit 1 MS/s SAR ADC with 7.72-ENOB

This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5μW with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.