Novel attributes and design considerations of effective oxide thickness in nano DG MOSFETs

Impacts of effective oxide thickness on a symmetric double-gate MOSFET with 9-nm gate length are studied, using full quantum simulation. The simulations are based on a self-consistent solution of the two-dimensional （2D） Poisson equation and the Schr6dinger equation within the non-equilibrium Green＇s function formalism. Oxide thickness and gate dielectric are investigated in terms of drain current, on-off current ratio, off current, sub-threshold swing, drain induced barrier lowering, transconductance, drain conductance, and voltage. Simulation results illustrate that we can improve the device performance by proper selection of the effective oxide thickness.

Equivalent oxide thickness scaling of Al_2O_3/Ge metal-oxide-semiconductor capacitors with ozone post oxidation

Aluminum-oxide films deposited as gate dielectrics on germanium （Ge） by atomic layer deposition were post oxidized in an ozone atmosphere. No additional interfacial layer was electron microscopy and X-ray photoelectron spectroscopy detected by the high-resolution cross-sectional transmission measurements made after the ozone post oxidation （OPO） treatment. Decreases in the equivalent oxide thickness of the OPO-treated Al2O3/Ge MOS capacitors were confirmed. Furthermore, a continuous decrease in the gate leakage current was achieved with increasing OPO treatment time. The results can be attributed to the film quality having been improved by the OPO treatment.

Performance analysis of silicon nanowire transistors considering effective oxide thickness of high-k gate dielectric

We have analyzed the effective oxide thickness （EOT） of the dielectric material for which we have optimum performance and the output characteristics of the silicon nanowire transistors by replacing the traditional Si02 gate insulator with a material that has a much higher dielectric constant （high-k） gate, materials like Si3N4, Al2O3, Y2O3 and HfO2. We have also analyzed the channel conductance, the effect of a change in thickness, the average velocity of the charge carrier and the conductance efficiency in order to study the performance of silicon nanowire transistors in the nanometer region. The analysis was performed using the Fettoy, a numerical simulator for ballistic nanowire transistors using a simple top of the barrier （Natori） approach, which is composed of several matlab scripts. Our results show that hafnium oxide （HfO2） gate insulator material provides good thermal stability, a high recrystallization temperature and better interface qualities when compared with other gate insulator materials; also the effective oxide thickness of lifO2 is found to be 0.4 nm.

Analytical modeling of oxide thickness variation of metals under high temperature solid-particle erosion

The paper presents a study of model development for predicting the oxide thickness on metals under high temperature solid-particle erosion.The model is created based on the theory of solid-particle erosion that characterizes the erosion damage as deformation wear and cutting wear,incorporating the effect of the oxide scale on the eroded surface under high temperature erosion.Then the instantaneous oxide thickness is the result of the synergetic effect of erosion and oxidation.The developed model is applied on a Ni-based Al-containing(Ni–Al)alloy to investigate the oxide thickness variation with erosion duration of the alloy at high temperatures.The results show that the thickness of the oxide scale on the alloy surface increases with the exposure time and temperature when the surface is not attacked by particles.However,when particles impact on the alloy surface,the oxide thickness is reduced,although oxidation is continuing.This indicates that oxidation does not benefit the erosion resistance of this alloy at high temperatures due to the low growth rate of the oxide.

Influences of different structures on the characteristics of H_2O-based and O_3-based La_xAl_yO films deposited by atomic layer deposition

H_2O-based and O_3-based La_xAl_yO nanolaminate films were deposited on Si substrates by atomic layer deposition（ALD）. Structures and performances of the films were changed by different barrier layers. The effects of different structures on the electrical characteristics and physical properties of the La_xAl_yO films were studied. Chemical bonds in the La_xAl_yO films grown with different structures and different oxidants were also investigated with x-ray photoelectron spectroscopy（XPS）. The preliminary testing results indicate that the La_xAl_yO films with different structures and different oxidants show different characteristics, including dielectric constant, equivalent oxide thickness（EOT）, electrical properties, and stability.

Analytical Modeling of Quantum Mechanical Tunneling in Germanium Nano-MOSFETS

A simple analytical model has been developed to study quantum mechanical effects （QME） in a germanium substrate MOSFET （metal oxide semiconductor field effect transistor）, which includes gate oxide tunneling considering the energy quantization effects in the substrate. Some alternate high dielectric constant materials to reduce the tunneling have also been studied. By comparing with the numerically reported results, the results match well with the existing reported work.

Study on the Effect of Two-Step Saturated Steam Heat Treatment Process on the Properties of Reconstituted Bamboo

With the aim of utilizing reconstituted bamboo as a carbon cycle oriented material,the improvement of physical and mechanical properties has been actively studied to solve using problems The saturated steam heat treatment process has been widely used in worldwide.With the development and exploration of this technology,two step satu-rated steam heat treatment process appears in some practical production,that is,affer a period of saturated steam heat treatment at a lower temperature,the bamboo bundles are taken out and seasoned for a period of time,and then put back into the heat tank again,and heated at a higher temperature for another period of time.During the two-step saturated steam heat treatment,the physical and mechanical properties of bamboo changed.However,the mechanism of two step saturated steam heat treatment has not been thoroughly discussed.For purpose that this paper all discuss and find out the mechanism of two step saturated steam heat treatment on the change of physical and mechanical properties of reconstituted bamboo.In this work,the one and two step saturated steam heat treat-ments were carried out according to the actual production parameters,and the physical and mechanical properties of the reconstituted bamboo board made of treated bamboo bundles were analyzed,including the color change,the thickness swelling(TS),modulus of elasticity(MOE),modulus of rupture(MOR)and shear strength.The results indicate that two-step saturated steam heat treatment is better than one step.Based on the detailed study of the chemical composition,crytalinity and micro morphologial characteristics of the heated bamboo bundles,it is further revealed that during two-step saturated steam heat treatment,oxygen air is added to the reaction system between the two heat treatment processes to further catalyze the oxidation of hemicellulose and enhance the crystal-linity of cellulose,so as to improve the properties of the final products.Our work has optimized the saturated steam heat treatment process which is widely used in industry,pointing out a new idea in the experimental and theoretical basis for the development of recombinant bamboo manufacturing industry.

探索Bi_(2)SeO_(5)的高介电性能:从块体到双层和单层

Bi_(2)SeO_(5)是一种具有优异电绝缘性能的范德华(vdW)层状介电材料,引起了极大关注.然而,目前关于Bi_(2)SeO_(5)的研究主要停留在实验层面,仍然缺乏对其原子级薄膜的介电性能的相关理论认识.本文通过第一性原理计算确定了Bi_(2)SeO_(5)的介电性能,发现其块体、双层和单层均具有超高平均介电常数(εr>20).研究表明,单层Bi_(2)SeO_(5)与双层Bi_(2)O_(2)Se之间的导带和价带能量偏移量均大于1 eV,表明单层Bi_(2)SeO_(5)依然可作为原子薄Bi_(2)O_(2)Se的良好介电层.此外,不同于h-BN或其他2D vdW绝缘体,Bi_(2)SeO_(5)的εr由其离子部分主导,且随着厚度的减小几乎保持不变.计算发现,单层Bi_(2)SeO_(5)的等效氧化层厚度可薄至0.3 n m,且单层Bi_(2)SeO_(5)在拉伸或压缩应变达到6%时均能保持高介电常数,这极大地促进了它与各种二维半导体的集成.本工作证明单层Bi_(2)SeO_(5)可以作为高性能二维电子器件良好的封装和介电层.

Comparative study of leakage power in CNTFET over MOSFET device

A comparison of the CNTFET device with the MOSFET device in the nanometer regime is reported. The characteristics of both devices are observed as varying the oxide thickness. Thereafter, we have analyzed the effect of the chiral vector and the temperature on the threshold voltage of the CNTFET device. After simulation on the HSPICE tool, we observed that the high threshold voltage can be achieved at a low chiral vector pair. It is also observed that the effect of temperature on the threshold voltage of the CNTFET is negligibly small. After that, we have analyzed the channel length variation and their impact on the threshold voltage of the CNTFET as well as MOSFET devices. We found an anomalous effect from our simulation result that the threshold voltage increases with decreasing the channel length in CNTFET devices; this is contrary to the well known short channel effect. It is observed that at below the 10 nm channel length, the threshold voltage is increased rapidly in the case of the CNTFET device, whereas in the case of the MOSFET device, the threshold voltage decreases drastically.

Compact analytical model of double gate junction-less field effect transistor comprising quantum-mechanical effect

We investigate the quantum-mechanical effects on the electrical properties of the double-gate j unction- less field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage, of DG-JLFET are analytically modeled and incorporated in the Duarte et al. model and then verified by TCAD simulation.

Analysis and impact of process variability on performance of junctionless double gate VeSFET

This paper presents an in-depth analysis of junctionless double gate vertical slit FET（JLDG VeSFET）device under process variability.It has been observed that junctionless FETs（JLDG VeSFET） are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric properties.Sensitivity analysis reveals that the slit width,oxide thickness,radius of the device,gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage,on current,off current and subthreshold slope（Ssub） as compared to its junction based counterpart i.e.MOSFET,because various short channel effects are well controlled in this device.The maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based device.However,variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET.

Combining a multi deposition multi annealing technique with a scavenging(Ti) to improve the high-k/metal gate stack performance for a gate-last process

ALD HfO2 films fabricated by a novel multi deposition multi annealing （MDMA） technique are inves- tigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing （D＆A）, devices receiving MDMA show a signif- icant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D＆A （while keeping the total annealing time and total dielectrics thickness the same）. Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be re- sponsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme.