Different charging behaviors between electrons and holes in Si nanocrystals embedded in SiN_x matrix by the influence of near-interface oxide traps

Si-rich silicon nitride films are prepared by plasma-enhanced chemical vapor deposition method, followed by thermal annealing to form the Si nanocrystals（Si-NCs） embedded in Si Nx floating gate MOS structures. The capacitance–voltage（C–V）, current–voltage（I–V）, and admittance–voltage（G–V） measurements are used to investigate the charging characteristics. It is found that the maximum flat band voltage shift（△VFB） due to full charged holes（～ 6.2 V） is much larger than that due to full charged electrons（～ 1 V）. The charging displacement current peaks of electrons and holes can be also observed by the I–V measurements, respectively. From the G–V measurements we find that the hole injection is influenced by the oxide hole traps which are located near the Si O2/Si-substrate interface. Combining the results of C–V and G–V measurements, we find that the hole charging of the Si-NCs occurs via a two-step tunneling mechanism. The evolution of G–V peak originated from oxide traps exhibits the process of hole injection into these defects and transferring to the Si-NCs.

New Forward Gated-Diode Technique for Separating Front Gate Interface- from Oxide-Traps Induced by Hot-Carrier-Stress in SOI-NMOSFETs

The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices

The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.

Effect of Snapback Stress on Gate Oxide Integrity of nMOSFET in 90nm Technology

By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with stress time. Oxide traps generated by stress will cause the increase of stress-induced leakage current and the decrease of Qbd （charge to breakdown）,and it may also cause the degradation of off-state drain leakage current. Stress-induced gate oxide damage is located not only in the drain side but also in the source side. The tertiary electrons generated by hot holes move toward Si-SiO2 interface under the electrical field toward the substrate,which explains the source side gate oxide damage.

Effect of substrate bias on negative bias temperature instability of ultra-deep sub-micro p-channel metal-oxide-semiconductor field-effect transistors

The effect of substrate bias on the degradation during applying a negative bias temperature （NBT） stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability （NBTI） is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electro,hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.

Characterization of Oxide Charge During Hot-Carrier Degradation of Ultrathin Gate pMOSFETs--Investigated by Charge Pumping Technique

The generation of oxide charge for 4nm pMOSFETs under hot-carrier stress is investigated by the charge pumping measurements.Firstly,the direct experimental evidences of logarithmic time dependence of hole trapping is observed for pMOSFETs with different channel lengths under hot-carrier stress.Thus,the relationships of oxide charge generation,including electron trapping and hole trapping effects,with different stress voltages and channel lengths are analyzed.It is also found that there is a two-step process in the generation of oxide charge for pMOSFETs.For a short stress time,electron trapping is predominant,whereas for a long stress time,hole trapping dominates the generation of oxide charge.

A Method to Separate Effects of Oxide-Trapped Charge and Interface-Trapped Charge on Threshold Voltage in pMOSFETs Under Hot-Carrier Stress

A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degradation in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under hot-carrier stress.Further,the experimental results verify the validness of this method.It is shown that,all three mechanisms of electron trapping effect,hole trapping effect and interface trap generation play important roles in p-channel MOSFETs degradation.It is noted that interface-trapped charge is still the dominant mechanism for hot-carrier-induced degradation in p-channel MOSFETs,while a significant contribution of oxide-trapped charge to threshold voltage is demonstrated and quantified.

Impact of switching frequencies on the TID response of SiC power MOSFETs

Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MOSFETs are investigated under different switching frequencies from 1 kHz to 10 MHz.A significant shift was observed in the threshold voltage as the frequency increased,which resulted in premature failure of the drain-source breakdown voltage and drain-source leakage current.The degradation is attributed to the high activation and low recovery rates of traps at high frequencies.The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching frequency of SiC power MOSFETs.

Bias dependence of a deep submicron NMOSFET response to total dose irradiation

Deep submicron n-channel metal-oxide-semiconductor field-effect transistors （NMOSFETs） with shallow trench isolation （STI） are exposed to ionizing dose radiation under different bias conditions. The total ionizing dose radiation induced subthreshold leakage current increase and the hump effect under four different irradiation bias conditions including the worst case （ON bias） for the transistors are discussed. The high electric fields at the corners are partly responsible for the subthreshold hump effect. Charge trapped in the isolation oxide, particularly at the Si/SiO2 interface along the sidewalls of the trench oxide creates a leakage path, which becomes a dominant contributor to the offstate drain-to-source leakage current in the NMOSFET. Non-uniform charge distribution is introduced into a threedimensional （3D） simulation. Good agreement between experimental and simulation results is demonstrated. We find that the electric field distribution along with the STI sidewall is important for the radiation effect under different bias conditions.

Total ionizing dose effect in an input/output device for flash memory

Input/output devices for flash memory are exposed to gamma ray irradiation. Total ionizing dose has been shown great influence on characteristic degradation of transistors with different sizes. In this paper, we observed a larger increase of off-state leakage in the short channel device than in long one. However, a larger threshold voltage shift is observed for the narrow width device than for the wide one, which is well known as the radiation induced narrow channel effect. The radiation induced charge in the shallow trench isolation oxide influences the electric field of the narrow channel device. Also, the drain bias dependence of the off-state leakage after irradiation is observed, which is called the radiation enhanced drain induced barrier lowing effect. Finally, we found that substrate bias voltage can suppress the off-state leakage, while leading to more obvious hump effect.

RADIATION EFFECT ON FLUORINATED SiO_2 FILMS

A systematic investigation of γ radiation effects in gate SiO2 as a function of thefluorine ion implantation conditions was performed. It has been found that thegeneration of interface states and oxide trapped charges in fluorinated MOSFETsdepends strongly on implantation conditions. The action of F in oxides is theconjunction of positive and negative effects. A model by forming St--F bonds tosubstitute the other strained bonds which easily become charge traps under irradiationand to relax the bond stress on St / SiOZ interface is use'd for experimental explanation.

Total ionizing dose radiation effects on NMOS parasitic transistors in advanced bulk CMOS technology devices

In this paper, total ionizing dose effect of NMOS transistors in advanced CMOS technology are exam- ined. The radiation tests are performed at 60Co sources at the dose rate of 50 rad （Si）/s. The investigation＇s results show that the radiation-induced charge buildup in the gate oxide can be ignored, and the field oxide isolation struc- ture is the main total dose problem. The total ionizing dose （TID） radiation effects of field oxide parasitic transistors are studied in detail. An analytical model of radiation defect charge induced by TID damage in field oxide is estab- lished. The I-V characteristics of the NMOS parasitic transistors at different doses are modeled by using a surface potential method. The modeling method is verified by the experimental I V characteristics of 180 nm commer- cial NMOS device induced by TID radiation at different doses. The model results are in good agreement with the radiation experimental results, which shows the analytical model can accurately predict the radiation response characteristics of advanced bulk CMOS technology device.

Gate length dependence of the shallow trench isolation leakage current in an irradiated deep submicron NMOSFET

The effects of gamma irradiation on the shallow trench isolation（STI）leakage currents in a 0.18μm technology are investigated.NMOSFETs with different gate lengths are irradiated at several dose levels.The threshold voltage shift is negligible in all of the devices due to the very thin oxide thickness.However,an increase in the off-state leakage current is observed for all of the devices.We believe that the leakage is induced by the drain-to-source leakage path along the STI sidewall,which is formed by the positive trapped charge in the STI oxide.Also, we found that the leakage is dependent on the device＇s gate length.The three-transistor model（one main transistor with two parasitic transistors）can provide us with a brief understanding of the dependence on gate length.