针对具有poly-Si1-x Ge x栅的应变Si Ge p型金属氧化物半导体场效应晶体管(PMOSFET),研究了其垂直电势与电场分布,建立了考虑栅耗尽的poly-Si1-x Ge x栅情况下该器件的等效栅氧化层厚度模型,并利用该模型分析了poly-Si1-x Ge x栅及应变S...针对具有poly-Si1-x Ge x栅的应变Si Ge p型金属氧化物半导体场效应晶体管(PMOSFET),研究了其垂直电势与电场分布,建立了考虑栅耗尽的poly-Si1-x Ge x栅情况下该器件的等效栅氧化层厚度模型,并利用该模型分析了poly-Si1-x Ge x栅及应变Si Ge层中Ge组分对等效氧化层厚度的影响.研究了应变Si Ge PMOSFET热载流子产生的机理及其对器件性能的影响,以及引起应变Si Ge PMOSFET阈值电压漂移的机理,并建立了该器件阈值电压漂移模型,揭示了器件阈值电压漂移随电应力施加时间、栅极电压、polySi1-x Ge x栅及应变Si Ge层中Ge组分的变化关系.并在此基础上进行了实验验证,在电应力施加10000 s时,阈值电压漂移0.032 V,与模拟结果基本一致,为应变Si Ge PMOSFET及相关电路的设计与制造提供了重要的理论与实践基础.展开更多
通过求解沟道的二维泊松方程得到沟道表面势和沟道反型层电荷,建立了高k栅介质小尺寸绝缘体上锗(Ge OI)p型金属氧化物半导体场效应晶体管(PMOSFET)的漏源电流解析模型.模型包括了速度饱和效应、迁移率调制效应和沟长调制效应,同时考虑...通过求解沟道的二维泊松方程得到沟道表面势和沟道反型层电荷,建立了高k栅介质小尺寸绝缘体上锗(Ge OI)p型金属氧化物半导体场效应晶体管(PMOSFET)的漏源电流解析模型.模型包括了速度饱和效应、迁移率调制效应和沟长调制效应,同时考虑了栅氧化层和埋氧层与沟道界面处的界面陷阱电荷、氧化层固定电荷对漏源电流的影响.在饱和区和非饱和区,漏源电流模拟结果与实验数据符合得较好,证实了模型的正确性和实用性.利用建立的漏源电流模型模拟分析了器件主要结构和物理参数对跨导、漏导、截止频率和电压增益的影响,对Ge OI PMOSFET的设计具有一定的指导作用.展开更多
Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) using P+ (phosphor ion) implantation technology is successfully fabricated. P+ implantation into SiGe virtual substrate induces a narrow de...Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) using P+ (phosphor ion) implantation technology is successfully fabricated. P+ implantation into SiGe virtual substrate induces a narrow defect region slightly below the SiGe/Si interface,which gives rise to strongly enhanced strain relaxation of SiGe virtual substrate. X-Ray Diffraction (XRD) tests show that the degree of relaxation of SiGe layer is 96% while 85% before implantation. After annealed,the sample appeared free of Threading Dislocation densities (TDs) within the SiGe layer to the limit of Trans-mission Electron Microscopy (TEM) analysis. Atomic Force Microscope (AFM) test of strained Si channel surface shows that Root Mean Square (RMS) is 1.1nm. The Direct Current (DC) characters measured by HP 4155B indicate that the maximum saturated transconductance is twice bigger than that of bulk Si PMOSFET.展开更多
文摘针对具有poly-Si1-x Ge x栅的应变Si Ge p型金属氧化物半导体场效应晶体管(PMOSFET),研究了其垂直电势与电场分布,建立了考虑栅耗尽的poly-Si1-x Ge x栅情况下该器件的等效栅氧化层厚度模型,并利用该模型分析了poly-Si1-x Ge x栅及应变Si Ge层中Ge组分对等效氧化层厚度的影响.研究了应变Si Ge PMOSFET热载流子产生的机理及其对器件性能的影响,以及引起应变Si Ge PMOSFET阈值电压漂移的机理,并建立了该器件阈值电压漂移模型,揭示了器件阈值电压漂移随电应力施加时间、栅极电压、polySi1-x Ge x栅及应变Si Ge层中Ge组分的变化关系.并在此基础上进行了实验验证,在电应力施加10000 s时,阈值电压漂移0.032 V,与模拟结果基本一致,为应变Si Ge PMOSFET及相关电路的设计与制造提供了重要的理论与实践基础.
文摘通过求解沟道的二维泊松方程得到沟道表面势和沟道反型层电荷,建立了高k栅介质小尺寸绝缘体上锗(Ge OI)p型金属氧化物半导体场效应晶体管(PMOSFET)的漏源电流解析模型.模型包括了速度饱和效应、迁移率调制效应和沟长调制效应,同时考虑了栅氧化层和埋氧层与沟道界面处的界面陷阱电荷、氧化层固定电荷对漏源电流的影响.在饱和区和非饱和区,漏源电流模拟结果与实验数据符合得较好,证实了模型的正确性和实用性.利用建立的漏源电流模型模拟分析了器件主要结构和物理参数对跨导、漏导、截止频率和电压增益的影响,对Ge OI PMOSFET的设计具有一定的指导作用.
基金Supported by the Funds of National Key Laboratory of Analog IC (2000JS09.3.1.DZ02).
文摘Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) using P+ (phosphor ion) implantation technology is successfully fabricated. P+ implantation into SiGe virtual substrate induces a narrow defect region slightly below the SiGe/Si interface,which gives rise to strongly enhanced strain relaxation of SiGe virtual substrate. X-Ray Diffraction (XRD) tests show that the degree of relaxation of SiGe layer is 96% while 85% before implantation. After annealed,the sample appeared free of Threading Dislocation densities (TDs) within the SiGe layer to the limit of Trans-mission Electron Microscopy (TEM) analysis. Atomic Force Microscope (AFM) test of strained Si channel surface shows that Root Mean Square (RMS) is 1.1nm. The Direct Current (DC) characters measured by HP 4155B indicate that the maximum saturated transconductance is twice bigger than that of bulk Si PMOSFET.
