Reliability evaluation on sense-switch p-channel flash

In this paper,the reliability of sense-switch p-channel flash is evaluated extensively.The endurance result indicates that the p-channel flash could be programmed and erased for more than 10000 cycles;the room temperature read stress shows negligible influence on the p-channel flash cell;high temperature data retention at 150℃ is extrapolated to be about 5 years and 53 years corresponding to 30% and 40% degradation in the drive current,respectively.Moreover,the electrical parameters of the p-channel flash at different operation temperature are found to be less affected.All the results above indicate that the sense-switch p-channel flash is suitable to be used as the configuration cell in flash-based FPGA.

Investigation on threshold voltage of p-channel GaN MOSFETs based on p-GaN/AlGaN/GaN heterostructure

The threshold voltage(V_(th))of the p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)is investigated via Silvaco-Atlas simulations.The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier heightΦ_(1,p),polarization charge density σ_(b),and equivalent unite capacitance C_(oc).It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V_(th),and threshold voltage|V_(th)|increases with the reduction in p-GaN doping concentration and the work-function of gate metal.Meanwhile,the increase in gate dielectric relative permittivity may cause the increase in threshold voltage|V_(th)|.Additionally,the parameter influencing output current most is the p-GaN doping concentration,and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5×10^(16) cm^(-3) at VGS=-12 V and VDS=-10 V.

A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

A novel low specific on-resistance （Ron,sp） silicon-on-insulator （SO1） p-channel lateral double-diffused metal-oxide semiconductor （pLDMOS） compatible with high voltage （HV） n-channel LDMOS （nLDMOS） is proposed. The pLDMOS is built in the N-type SO1 layer with a buried P-type layer acting as a current conduction path in the on-state （BP SOl pLD- MOS）. Its superior compatibility with the HV nLDMOS and low voltage （LV） complementary metal-oxide semiconductor （CMOS） circuitry which are formed on the N-SOl layer can be obtained. In the off-state the P-buried layer built in the NSOI layer causes multiple depletion and electric field reshaping, leading to an enhanced （reduced） surface field （RESURF） effect. The proposed BP SO1 pLDMOS achieves not only an improved breakdown voltage （BV） but also a significantly reduced Ron,sp. The BV of the BP SO1 pLDMOS increases to 319 V from 215 V of the conventional SO1 pLDMOS at the same half cell pitch of 25 μm, and Ron,sp decreases from 157 mΩ.cm2 to 55 mΩ.cm2. Compared with the PW SO1 pLDMOS, the BP SO1 pLDMOS also reduces the Ron,sp by 34% with almost the same BV.

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel low-density metal-oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-density metal- oxide semiconductor （LDMOS）. Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state （on-state） BV of the SOI p-channel LDMOS can reach 741 （620） V in the 3μm-thick buried oxide layer, 50μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability （NBTI） has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors （MOSFETs）. The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^＋ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^＋ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^＋ generated during NBTI stress.

A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer

A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator（SOI） devices. In this new structure, the conventional buried oxide（BOX） in an SOI device is split into two sections： the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer（NPCL）, is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage（BV） is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor（LDMOS） and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance（Ron,sp） is reduced by 69% in comparison to the conventional structure.

Investigation of performance-enhanced GaN-based E-mode pchannel MOSFET with pre-ohmic-annealing treatment

Pre-ohmic-annealing(POA)treatment of P-GaN/AlN/AlGaN epitaxy under N_(2)atmosphere was demonstrated to effectively achieve good p-type ohmic contact as well as decreased epitaxy sheet resistance.Ohmic contact resistance(Rc)extracted by transfer length method reduced from 38 to 23Ω·mm with alleviated contact barrier height from 0.55 to 0.51 eV after POA treatment.X-ray photoelectron spectroscopy and Hall measurement confirmed that POA treatment was able to reduce surface state density and improve the hole concentration of p-GaN.Due to the decreased Rc and improved two-dimensional hole gas(2DHG)density,an outstanding-performance GaN E-mode p-channel MOSFET was successfully realized.

利用瑞利面波提高近地表横波速度精度的方法

二维油气地震勘探中,由于受野外施工条件、成本效益等诸多因素限制,地震记录的野外采集道间距往往较大,这种地震记录往往容易产生空间假频,降低其频率—速度谱信噪比。为此,提出利用小波变换良好的时频分析特性,对大时空采样记录进行基于小波基的道内插值,以提高P-SV转换波地震资料中的瑞利面波频散高频信息的精度,从而提高反演表层横波速度结构精度,提高P-SV转换波的横波静校正精度。对理论模型和实际数据进行的验证计算表明,基于小波基的道内插值方法具有抗假频性,瑞利面波基阶频散曲线拐点更清晰,高频段能量更加集中,反演的横波速度精度更高,取得了较好效果。

用于GaN CMOS集成技术的p型GaN欧姆接触研究

通过金属叠层结构、蒸发-合金工艺条件的优化调整,实现了低接触电阻率、高稳定的p型GaN欧姆接触技术,并研究分析了电极金属在合金过程中的扩散行为。测试结果显示,改进后的p型GaN欧姆接触电阻为11.9Ω·mm,比导通电阻率为3.9×10^(-5)Ω·cm^(2),同时在250℃以内的高温环境中欧姆特性不会发生退化。在此基础上,采用低损伤凹槽栅刻蚀、叠层栅介质沉积等工艺研制出增强型p沟道GaN晶体管器件,器件的阈值电压为-1.2 V(V_(GS)=VDS,IDS=10μA/mm),漏极电流密度为-5.6 mA/mm,导通电阻为665Ω·mm(V_(GS)=-8 V,V_(DS)=-2 V)。优异的p型GaN欧姆接触技术为高性能GaN p沟道器件的研制以及GaN CMOS集成技术的小型化、智能化、高速化发展奠定了重要基础。

氮化镓基单片功率集成技术

宽禁带、高临界击穿电场和高饱和电子速度的材料优越性,以及铝镓氮/氮化镓(Al GaN/GaN)异质结能通过极化不连续性在其界面极化诱导出具有高浓度、高迁移率的二维电子气并制备出高电子迁移率晶体管,使氮化镓器件正成为下一代功率和射频应用领域的新型高性能电子器件。氮化镓基单片功率集成技术是减小寄生电感影响、提升集成电路开关速度、降低系统功耗和实现系统小型化的关键技术。该文围绕氮化镓单片功率集成技术,对p/n双极性沟道异质结外延结构、单片异质集成、全氮化镓集成电路和p沟道器件关键技术的研究进展进行了全面分析。

多波地震联合技术精细雕刻隐蔽河道砂体——以四川盆地西北部ZT地区沙溪庙组为例

四川盆地陆相致密砂岩气资源丰富,是目前天然气增储上产的重要领域,但侏罗系沙溪庙组沙一段河道砂体纵向多期叠置,横向同期交汇且河道砂体类型多样,隐蔽性强,形成了复杂多变的地震反射特征,准确刻画河道砂体难度极大。为了解决四川盆地西北部(以下简称川西北)ZT地区沙溪庙组一段(以下简称沙一段)多期河道砂体及储层刻画不清晰、精度低的问题,采用新采集的三维地震三分量转换横波(PS波)资料,结合PP波叠前数据和常规叠后地震资料,在正演模拟基础上,形成了多波地震联合雕刻河道砂体关键技术,并分析了河道砂体多波地震响应特征随砂体孔隙度的变化规律。研究结果表明:(1)砂体顶界PP波地震响应随孔隙度增大由强波峰转变为强波谷,而PS波地震响应不随物性变化发生极性反转,基于横波对岩性的刻画可有效识别多期隐蔽河道砂体;(2)相较反映横波阻抗变化率的叠前P-G属性,PS波振幅能量更聚焦,雕刻的河道砂体横向展布特征更清晰,边界更清楚;(3)叠前P-G属性具有更高的纵向分辨率,有利于区分叠置砂体,并落实砂体的发育期次。结论认为,多波地震技术联合充分发挥P-G的高分辨率优势确定纵向砂体发育期次,发挥PS波横向连续性优势刻画横向边界,实现了ZT地区沙一段河道砂体的完整精细雕刻,生产应用效果显著,并为该区井位部署和储量升级提供了有力技术支撑,为四川盆地陆相致密砂岩气规模效益开发奠定了坚实的基础,同时有力推进了多波地震勘探技术的发展。

一种基于PJFET输入的高压摆率集成运算放大器

基于双极型集成工艺设计并制作了一种高压摆率、低输入偏置电流、低输入失调电流的运算放大器。输入级采用p沟道结型场效应晶体管(PJFET)共源结构,有利于减小输入偏置电流,提高信号接收的灵敏度,实现高输入阻抗、低偏置电流、低输入失调电流和高压摆率。增益级采用常规的共射放大电路结构。输出级采用互补推挽输出结构,提升了驱动负载的能力,并克服交越失真。测试结果表明:在电源电压±15 V、25℃环境温度下,开环电压增益为114.49 dB,正压摆率为12.33 V/μs,负压摆率为-9.76 V/μs,输入偏置电流为42.52 pA,输入失调电流为4.23 pA,输出电压摆幅为-13.56~14.16 V,共模抑制比为105.56 dB,电源抑制比为107.91 dB。

A novel 2 T P-channel nano-crystal memory for low power/high speed embedded NVM applications

We introduce a novel 2 T P-channel nano-crystal memory structure for low power and high speed embedded non-volatile memory（NVM） applications.By using the band-to-band tunneling-induced hot-electron （BTBTIHE） injection scheme,both high-speed and low power programming can be achieved at the same time. Due to the use of a select transistor,the ＂erased states＂ can be set to below 0 V,so that the periphery HV circuit （high-voltage generating and management） and read-out circuit can be simplified.Good memory cell performance has also been achieved,including a fast program/erase（P/E） speed（a 1.15 V memory window under 10μs program pulse）,an excellent data retention（only 20%charge loss for 10 years）.The data shows that the device has strong potential for future embedded NVM applications.

脊柱微创通道镜辅助下融合术对腰椎退行性疾病患者血清SP、β-EP的影响

目的:探讨与分析脊柱微创通道镜辅助下融合术对腰椎退行性疾病患者血清P物质(SP)、β-内啡肽(β-EP)的影响。方法:选取2020年1月-2022年12月我院收治的130例腰椎退行性疾病患者为研究对象,采用随机数字表法将其分为研究组与对照组,各65例。对照组采用后外侧植骨融合手术治疗,研究组采用脊柱微创通道镜辅助下融合术治疗,记录2组围手术期指标、术后1个月并发症的发生情况、治疗效果SP、β-EP变化情况。结果:和对照组比较,研究组的术中失血量、术后引流量均更少,在手术及术后住院方面花费的时间均更短,组间差异有统计学意义(P<0.05)。2组术后1个月的SP、β-EP均少于术前1 d,组间差异有统计学意义(P<0.05),研究组术后1个月的SP、β-EP均少于对照组,组间差异有统计学意义(P<0.05)。研究组术后1个月内的脑脊液渗漏、切口感染、神经根痛、腰椎间隙感染等不良反应发生率为1.54%,低于对照组的10.77%,差异有统计学意义(P<0.05)。术后1个月,研究组的治疗总有效率为96.92%,高于对照组的84.62%,差异有统计学意义(P<0.05)。结论:脊柱微创通道镜辅助下融合术在腰椎退行性疾病的应用能促进患者康复,减少对患者的创伤,减少SP、β-EP,还能降低患者的并发症发生率,提高患者的总体疗效。

High threshold voltage enhancement-mode GaN p-FET with Sirich LPCVD SiN_(x) gate insulator for high hole mobility

In this work,the GaN p-MISFET with LPCVD-SiN_(x) is studied as a gate dielectric to improve device performance.By changing the Si/N stoichiometry of SiN_(x),it is found that the channel hole mobility can be effectively enhanced with Si-rich SiN_(x) gate dielectric,which leads to a respectably improved drive current of GaN p-FET.The record high channel mobility of 19.4 cm2/(V∙s)was achieved in the device featuring an Enhancement-mode channel.Benefiting from the significantly improved channel mobility,the fabricated E-mode GaN p-MISFET is capable of delivering a decent-high current of 1.6 mA/mm,while simultaneously featuring a negative threshold-voltage(VTH)of–2.3 V(defining at a stringent criteria of 10μA/mm).The device also exhibits a well pinch-off at 0 V with low leakage current of 1 nA/mm.This suggests that a decent E-mode operation of the fabricated p-FET is obtained.In addition,the VTH shows excellent stability,while the threshold-voltage hysteresisΔVTH is as small as 0.1 V for a gate voltage swing up to–10 V,which is among the best results reported in the literature.The results indicate that optimizing the Si/N stoichiometry of LPCVD-SiN_(x) is a promising approach to improve the device performance of GaN p-MISFET.

基于地震槽波与纵波的采煤工作面高应力区探测技术

随着煤矿生产区域向深部转移,开采深度持续增加,开采条件趋于复杂,冲击地压灾害趋于严重,迫切需要能够准确探测采煤工作面高应力区空间分布的探测手段。通过单轴压缩试验,研究了煤岩样在单轴压缩下的地震纵波速度变化,发现在单轴压缩下的弹性阶段,煤岩样轴向地震纵波速度随着应力增加而升高,直至煤岩块遭受破坏,波速迅速下降,地震波速与应力的响应曲线表明在煤岩样弹性阶段地震纵波与应力呈正相关关系;同时也尝试研究了单轴压缩条件下地震槽波速度与应力的响应曲线特征,发现地震槽波与应力呈正相关关系,也可用于采煤工作面高应力区探查;拟将地震槽波与纵波联合用于探测应力集中区。选取了地质条件简单的采煤工作面开展高应力探测试验,在试验数据中提取了纵波的初至速度和槽波特定频率下的速度,经过CT层析成像后形成波速等值线图,然后结合巷道相关资料对比分析,分别圈出各自的高速区,并按照地震波速与应力的正相关关系,将高速区解释为高应力区,最终把两者的重叠区域作为工作面冲击地压高风险区。经钻孔和回采验证:在应力重叠区施工钻孔时煤粉量明显偏大,易缩孔;回采通过应力重叠区时,巷道变形相对较大,“煤炮”时有发生。联合勘探试验表明槽波可用来探测采煤工作面的高应力区,与纵波相结合能够克服单一物探手段的局限性,更准确地探测冲击地压矿井采煤工作面的高应力区。

基于DDS信号和插值法的FBG解调系统研究

针对F-P滤波器解调法容易产生漂移与校正成本较高的问题,本文采用FPGA和光开关搭建了F-P滤波器多通道共振解调系统,该系统利用DDS信号生成特定的三角波驱动电压,通过串联多维参考FBG实现基于插值法对波长-时间的动态标定,设定了3种动态标定模式,包含线性关系和二次关系的标定。利用FPGA控制光开关实现快速切换模式与参考波长、待测波长信号的分步采集,3种模式100 Hz平均偏差分别为0.02802 nm、0.01814 nm、0.0109 nm。研究结果表明,在单位电压(1 V)下,相对于静态标定,误差降低45%以上,提高解调精度并且降低校正成本,同时解决参考与待测波长数值过近时容易导致的误判问题。

30伏P沟VDMOS场效应管的设计

对于IRF7705型30伏P沟VDMOSFET进行了结构优化设计.给出了该器件的纵向结构和横向结构参数及材料的物理参数.较系统地分析了VDMOSFET的几个重要参数,重点讨论了P沟VDMOSFET的外延层电阻率、外延层厚度、N体区扩散浓度以及各个参数之间的关系,对该类器件的实际生产有一定的指导作用.

工艺偏差下PMOS器件的负偏置温度不稳定效应分布特性

当器件特征尺寸进入纳米级，负偏置温度不稳定性（NBTI）效应和工艺偏差都会导致p 型金属氧化层半导体（PMOS）器件性能和可靠性的下降.基于反应-扩散（R-D）模型，本文分析了工艺偏差对NBTI效应的影响；在此基础上将氧化层厚度误差和初始阈值电压误差引入到R-D模型中，提出了在工艺偏差下PMOS器件的NBTI效应统计模型.基于65 nm工艺，首先蒙特卡罗仿真表明在工艺偏差和NBTI效应共同作用下， PMOS器件阈值电压虽然会随着应力时间增大而沿着负方向增加，但是阈值电压的匹配性却随着时间推移而变好；其次验证本文提出的统计模型准确性，以R-D模型为参考，在104 s应力时间内， PMOS器件阈值电压退化量平均值和均方差的最大相对误差分别为0.058%和0.91%；最后将此模型应用到电流舵型数模转换器中，仿真结果显示在工艺偏差和NBTI效应共同作用下，数模转换器的增益误差会随着应力时间的推移而增大，而线性误差会逐渐减小.

P型掺锌硫化铜铝透明导电薄膜的制备和性能研究

采用渠道火花烧蚀技术,在普通玻璃基板上制备掺锌硫化铜铝CuAl0.90Zn0.10S2透明导电薄膜。运用X射线衍射法(XRD)和原子力显微镜(AFM)分析薄膜的晶体结构和表面形貌。研究不同的制备条件对薄膜光电性能的影响。结果显示,薄膜表面平整致密,均为p型导电。氩气压强和基板温度对薄膜的电阻率和载流子浓度具有显著影响,例如,随着氩气压强增加,电阻率会先降低再上升,而载流子浓度则先增加再降低。在优化的制备条件下,薄膜的电阻率最小值为0.2Ω.cm,载流子浓度为6.67×1018cm-3,载流子迁移率最大为1.06 cm2V-1S-1。在基板温度Ts=500℃时,获得了室温下最高电导率为50.9 S.cm-1的薄膜。薄膜可见光区域的平均透射率大于60%。