The frame structure of a process design kit （PDK） is described in detail, and a practical design method for PDK is presented. Based on this method, a useful SMIC 65 nm PDK has been successfully designed and realized...The frame structure of a process design kit （PDK） is described in detail, and a practical design method for PDK is presented. Based on this method, a useful SMIC 65 nm PDK has been successfully designed and realized, which is applicable to native EDA software of Zeni. The design process and difficulties of PDK are introduced by developing and analyzing these parameterized cell （Pcell） devices （MOS, resistor, etc.）. A structured design method was proposed to implement Pcell, which makes thousands upon thousands of source codes of Pcell concise, readable, easy-to-upkeep and transplantable. Moreover, a Pcase library for each Pcell is designed to verify the Pcell in batches. By this approach, the Pcell can be verified efficiently and the PDK will be more reliable and steady. In addition, the component description format parameters and layouts of the Pcell are optimized by adding flexibility and improving performance, which benefits analog and custom IC designers to satisfy the demand of design. Finally, the SMIC 65 nm PDK was applied to IC design. The results indicate that the SMIC 65 nm PDK is competent to support IC design.展开更多
基金Project supported by the National Major Specialized Program of China(No.2008ZX01035-001-08)
文摘The frame structure of a process design kit （PDK） is described in detail, and a practical design method for PDK is presented. Based on this method, a useful SMIC 65 nm PDK has been successfully designed and realized, which is applicable to native EDA software of Zeni. The design process and difficulties of PDK are introduced by developing and analyzing these parameterized cell （Pcell） devices （MOS, resistor, etc.）. A structured design method was proposed to implement Pcell, which makes thousands upon thousands of source codes of Pcell concise, readable, easy-to-upkeep and transplantable. Moreover, a Pcase library for each Pcell is designed to verify the Pcell in batches. By this approach, the Pcell can be verified efficiently and the PDK will be more reliable and steady. In addition, the component description format parameters and layouts of the Pcell are optimized by adding flexibility and improving performance, which benefits analog and custom IC designers to satisfy the demand of design. Finally, the SMIC 65 nm PDK was applied to IC design. The results indicate that the SMIC 65 nm PDK is competent to support IC design.
