This article introduces the aim,significance and functions of Police Document Full-text Database.It also gives a detailed description of its data organization and data flow.
SOZL (structured methodology + object-oriented methodology + Z language) is a language that attempts to integrate structured method, object-oriented method and formal method. The core of this language is predicate dat...SOZL (structured methodology + object-oriented methodology + Z language) is a language that attempts to integrate structured method, object-oriented method and formal method. The core of this language is predicate data flow diagram (PDFD). In order to eliminate the ambiguity of predicate data flow diagrams and their associated textual specifications, a formalization of the syntax and semantics of predicate data flow diagrams is necessary. In this paper we use Z notation to define an abstract syntax and the related structural constraints for the PDFD notation, and provide it with an axiomatic semantics based on the concept of data availability and functionality of predicate operation. Finally, an example is given to establish functionality consistent decomposition on hierarchical PDFD (HPDFD).展开更多
This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the ...This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and l Gb/s throughput in 1.8 V 0.18μm standard cell complementary metal-oxide-semiconductor （CMOS） process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder （PDFD） with 39% area reduction.展开更多
文摘This article introduces the aim,significance and functions of Police Document Full-text Database.It also gives a detailed description of its data organization and data flow.
文摘SOZL (structured methodology + object-oriented methodology + Z language) is a language that attempts to integrate structured method, object-oriented method and formal method. The core of this language is predicate data flow diagram (PDFD). In order to eliminate the ambiguity of predicate data flow diagrams and their associated textual specifications, a formalization of the syntax and semantics of predicate data flow diagrams is necessary. In this paper we use Z notation to define an abstract syntax and the related structural constraints for the PDFD notation, and provide it with an axiomatic semantics based on the concept of data availability and functionality of predicate operation. Finally, an example is given to establish functionality consistent decomposition on hierarchical PDFD (HPDFD).
基金the National Science Foundation for Creative Research Groups （60521002）Shanghai Natural Science Foundation （037062022）.
文摘This article presents an M-algorithm （MA） decoder with 4 survival paths （MA4） for Institute of Electrical and Electronics Engineers （IEEE） 802.3ab 1000BASE-T gigabit Ethernet （GbE） transceiver. To fulfill the entire requirements, various methods were introduced to accelerate the MA4 decoder while retaining the desired high performance and low complexity. Optimized look-ahead architecture was employed to solve the critical path problem with minimal gate consumption. Symbol compression methods saved registers during pipeline stages. A sorting network accelerated the kernel sorting operation at low hardware cost by utilizing the special characteristics of MA4. Simulations and synthesis results show that the proposed decoder achieves 125 MHz clock frequency and l Gb/s throughput in 1.8 V 0.18μm standard cell complementary metal-oxide-semiconductor （CMOS） process. It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder （PDFD） with 39% area reduction.
