An Investigation of Power Converters Fed BLDC Motor for Adjustable Speed

This paper reports the converter topologies which are employed for better Power Factor Correction at the input side. The Power Factor Correction is an important factor when considering the Power Quality. Based on the converter topologies, the Bridgeless converters are preferred in order to reduce the number of switching devices, losses associated with it and improve the Power Quality further more. This paper investigates about the Power Factor performances and conduction losses of the Bridgeless Power Factor Corrector Converters which see through the benefits and limitations by analyzing the Bridgeless Buck-Boost Converter, Bridgeless SEPIC converter and Bridgeless CUK converter. The resultant voltage is fed to the BLDC motor which is rapidly replacing the Induction motor for its better operating characteristics. These strategies are being analyzed using the MATLAB/Simulink software and the results are verified through the experimental analysis. The converter choice is preferred through the performance characteristics and Power Factor Correction at the supply. The Power Factor obtained should be within the acceptable limits under IEC 61000-3-2 standards.

A Novel 5-level Flying Capacitor Bridgeless PFC Converter Based on Cost-effective Low-voltage eGaN FETs

In this study,a type of multilevel flying capacitor bridgeless PFC converter is proposed that permits the use of economical and efficient 100 V GaN transistors.Compared with the popular two-level totem-pole bridgeless PFC converters achieved using the much more expensive 650 V GaN devices,this new design has several distinct advantages:lower component costs,lower dv/dt,lower power losses,and reduced concerns about device reliability.A 1.6 kW,5-level PFC converter prototype is designed and fabricated with an efficiency of 99.18%and a power factor of 0.99,which are experimentally demonstrated.The operation principle,design considerations,control strategy and experimental results are discussed.

Principle of designing slope compensation in PFC Boost converter

Due to wide input fluctuation with line frequency of 50 Hz, power-factor-correction （PFC） Boost converters tend to exhibit fast-scale instability over time domain. The traditional remedy is to impose slope compensation so as to weaken or eliminate this instability. A theoretical principle on the implementation of slope compensation signal is still lacking. Empirical design will induce over compensation frequently, resulting in a large decrease of power factor. In order to tackle this issue, by constructing the discrete-time iterative map of the PFC Boost converter from the viewpoint of bifurcation control theory of nonlinear systems, consequently, the criterion of critical stability for the PFC circuit can be established. Based on this stability criterion, appropriate design of slope compensation can be achieved. Our work indicates that 3 main circuit parameters （i.e. switching cycle, output reference voltage and inductor） determine the effective amplitude design of the slope compensation signal. The results, validated by a large quantity of analytical and numerical studies, show that appropriate slope compensation can be effective in weakening （or controlling） fast-scale bifurcation while maintaining a rather high input power factor.