在实时性导通控制中,常用过零检测法和锁相环法。比较了过零检测法、三相单同步、三相双同步坐标系锁相环法,提出了适用于混合式固态交流断路器(Hybird Solid State Switch,HSSS)的单相自解耦锁相策略,并给出了数学模型和控制模型,通过...在实时性导通控制中,常用过零检测法和锁相环法。比较了过零检测法、三相单同步、三相双同步坐标系锁相环法,提出了适用于混合式固态交流断路器(Hybird Solid State Switch,HSSS)的单相自解耦锁相策略,并给出了数学模型和控制模型,通过分析稳态性能和动态性能得出了控制参数。在MATLAB/Simulink环境下构建上述实时性控制模型与HSSS模型,通过仿真与最优化分析验证了单相自解耦锁相环在各种电网电压工况下具有良好的锁相效果,能够实现HSSS的基本功能,满足实时性控制要求。展开更多
CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a bri...CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.展开更多
文摘在实时性导通控制中,常用过零检测法和锁相环法。比较了过零检测法、三相单同步、三相双同步坐标系锁相环法,提出了适用于混合式固态交流断路器(Hybird Solid State Switch,HSSS)的单相自解耦锁相策略,并给出了数学模型和控制模型,通过分析稳态性能和动态性能得出了控制参数。在MATLAB/Simulink环境下构建上述实时性控制模型与HSSS模型,通过仿真与最优化分析验证了单相自解耦锁相环在各种电网电压工况下具有良好的锁相效果,能够实现HSSS的基本功能,满足实时性控制要求。
基金supported by the Pioneer Hundred Talents Program,Chinese Academy of Sciences.
文摘CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.
