The design and implementation of a CMOS LC VCO with 3. 2-6. 1GHz tuning range are presented. This is achieved by enhancing the tuning capability of the binary-weighted band-switching MIM capacitor. The circuit has bee...The design and implementation of a CMOS LC VCO with 3. 2-6. 1GHz tuning range are presented. This is achieved by enhancing the tuning capability of the binary-weighted band-switching MIM capacitor. The circuit has been implemented in a 0. 18μm RF/Mixed-Signal CMOS process. The measured phase noise is - 101.67dBc/Hz at 1MHz offset from a 5.5GHz carrier,and the VCO core draws 9.69mA current from a 1.8V supply.展开更多
A low jitter phase-locked loop （PLL） that does not need analog resistors and capacitors is designed and fabrica- ted in a 90nm CMOS digital process. The metal parasitic capacitor is used in the PLL loop filter. Test...A low jitter phase-locked loop （PLL） that does not need analog resistors and capacitors is designed and fabrica- ted in a 90nm CMOS digital process. The metal parasitic capacitor is used in the PLL loop filter. Test results show that when the PLL is locked on 1. 989GHz, the RMS jitter is 3. 7977ps, the peak-to-peak jitter is 31. 225ps, and the power con- sumption is about 9mW. The locked output frequency range is from 125MHz to 2.7GHz.展开更多
A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process. The VCO has a 16.15% tuning range （from 1. 8998 to 2. 2335GHz） through a combination of analog and digital tun...A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process. The VCO has a 16.15% tuning range （from 1. 8998 to 2. 2335GHz） through a combination of analog and digital tuning techniques （4-bit binary switch-capacitor array）. The measured phase noise is - 118.17dBc/Hz at a 1MHz offset from a 2. 158GHz carrier. With the presented improved switch,the phase noise varies no more than 3dB at different digital control bits. The phase noise changes only by about 2dB in the tuning range because of the pn-junctions as the varactors. The VCO draws a current of about 2. lmA from a 1.8V power supply and works normally with a 1.5V power supply.展开更多
This paper presents a VHF CMOS VCO. The most significant improvement on the VCO is that the cross-coupled MOSFET pairs are divided into several switchable parts so the characteristics can compensate the state change t...This paper presents a VHF CMOS VCO. The most significant improvement on the VCO is that the cross-coupled MOSFET pairs are divided into several switchable parts so the characteristics can compensate the state change that results from the frequency tuning of the oscillator. This VCO is implemented in 0, 18μm CMOS with a core area of about 550μm × 700μm. The test results show that the tuning range covers 31-111MHz with a power consumption between 0.3-6. 9mW and a phase noise at a 100kHz offset of about - 110dBc/Hz.展开更多
By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes ...By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.展开更多
This paper aims to introduce a quadrature VCO (voltage control oscillator) which applies superharmonic coupling. The presented quadrature VCO is suitable to be used, both with 2 × subharmonic mixers, as well as 4...This paper aims to introduce a quadrature VCO (voltage control oscillator) which applies superharmonic coupling. The presented quadrature VCO is suitable to be used, both with 2 × subharmonic mixers, as well as 4×subharmonic mixers. It would be impossible to avoid the presence of harmonics in CMOS VCO circuits. These harmonics are in general, undesirable signals which tend to accompany the desired fundamental signal. There are common-mode nodes (similar to those in the two source nodes in a cross-coupled VCO) in deferential VCO at which higher-order harmonics are present while the fundamental is absent in essence. We can make use of these second-order harmonics which are present at the common-mode nodes of two VCO in order to implement a quadrature connection between the fundamental outputs. The technique through which this is done is called superharmonic coupling. This CMOS quadrature VCO which applies active superharmonic coupling puts an excellent performance in show, with an output power –0.942 dBm for fundamental and –9.751 dBm for subharmonic, phase noise –107.2 dBc/Hz for fundamental and –114.8 dBc/Hz at a 1MHz offset. All of circuit applied are designed and simulated by ADS, 2008.展开更多
This paper presents a low-phase-noise LC voltage-controlled oscillator (LC-VCO) with top resistive biasing in subthreshold region. The subthreshold LC-VCO has low-power and low-phase-noise due to its high transconduct...This paper presents a low-phase-noise LC voltage-controlled oscillator (LC-VCO) with top resistive biasing in subthreshold region. The subthreshold LC-VCO has low-power and low-phase-noise due to its high transconductance efficiency and low gate bias condition. The top resistive biasing has more benefit with the feature of phase noise than MOS current source since it can support the low-noise characteristics and large output swing. The LC-VCO designed in 130-nm CMOS process with 0.7-V supply voltage achieves phase noise of -116 dBc/Hz at 200 kHz offset with tuning range of 398 MHz to 408 MHz covering medical implant communication service (MICS) band.展开更多
This paper introduces a modified design of CMOS dynamic Phase Frequency Detector (PFD). The proposed PFD circuit (PPFD) is designed, simulated and the results obtained are analyzed. In order to reduce dead zone, inter...This paper introduces a modified design of CMOS dynamic Phase Frequency Detector (PFD). The proposed PFD circuit (PPFD) is designed, simulated and the results obtained are analyzed. In order to reduce dead zone, internal signal routing is used in the PPFD circuit. To extend, Phase Locked Loop (PLL) is designed and it is verified with two different Frequency Divider (FD) circuits. There is a decrease in area of the PPFD circuit with 16 transistors and dissipates power of 40.8 pW for 1.2 V power supply. The pre-layout simulation result shows that the PPFD circuit has an elimination of a dead zone. Further, it works with the high speed and reduced power operated in the reference frequency of 50 MHz and the feedback frequency up to 4 GHz.展开更多
文摘The design and implementation of a CMOS LC VCO with 3. 2-6. 1GHz tuning range are presented. This is achieved by enhancing the tuning capability of the binary-weighted band-switching MIM capacitor. The circuit has been implemented in a 0. 18μm RF/Mixed-Signal CMOS process. The measured phase noise is - 101.67dBc/Hz at 1MHz offset from a 5.5GHz carrier,and the VCO core draws 9.69mA current from a 1.8V supply.
文摘A low jitter phase-locked loop （PLL） that does not need analog resistors and capacitors is designed and fabrica- ted in a 90nm CMOS digital process. The metal parasitic capacitor is used in the PLL loop filter. Test results show that when the PLL is locked on 1. 989GHz, the RMS jitter is 3. 7977ps, the peak-to-peak jitter is 31. 225ps, and the power con- sumption is about 9mW. The locked output frequency range is from 125MHz to 2.7GHz.
文摘A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process. The VCO has a 16.15% tuning range （from 1. 8998 to 2. 2335GHz） through a combination of analog and digital tuning techniques （4-bit binary switch-capacitor array）. The measured phase noise is - 118.17dBc/Hz at a 1MHz offset from a 2. 158GHz carrier. With the presented improved switch,the phase noise varies no more than 3dB at different digital control bits. The phase noise changes only by about 2dB in the tuning range because of the pn-junctions as the varactors. The VCO draws a current of about 2. lmA from a 1.8V power supply and works normally with a 1.5V power supply.
文摘This paper presents a VHF CMOS VCO. The most significant improvement on the VCO is that the cross-coupled MOSFET pairs are divided into several switchable parts so the characteristics can compensate the state change that results from the frequency tuning of the oscillator. This VCO is implemented in 0, 18μm CMOS with a core area of about 550μm × 700μm. The test results show that the tuning range covers 31-111MHz with a power consumption between 0.3-6. 9mW and a phase noise at a 100kHz offset of about - 110dBc/Hz.
文摘By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.
文摘This paper aims to introduce a quadrature VCO (voltage control oscillator) which applies superharmonic coupling. The presented quadrature VCO is suitable to be used, both with 2 × subharmonic mixers, as well as 4×subharmonic mixers. It would be impossible to avoid the presence of harmonics in CMOS VCO circuits. These harmonics are in general, undesirable signals which tend to accompany the desired fundamental signal. There are common-mode nodes (similar to those in the two source nodes in a cross-coupled VCO) in deferential VCO at which higher-order harmonics are present while the fundamental is absent in essence. We can make use of these second-order harmonics which are present at the common-mode nodes of two VCO in order to implement a quadrature connection between the fundamental outputs. The technique through which this is done is called superharmonic coupling. This CMOS quadrature VCO which applies active superharmonic coupling puts an excellent performance in show, with an output power –0.942 dBm for fundamental and –9.751 dBm for subharmonic, phase noise –107.2 dBc/Hz for fundamental and –114.8 dBc/Hz at a 1MHz offset. All of circuit applied are designed and simulated by ADS, 2008.
文摘This paper presents a low-phase-noise LC voltage-controlled oscillator (LC-VCO) with top resistive biasing in subthreshold region. The subthreshold LC-VCO has low-power and low-phase-noise due to its high transconductance efficiency and low gate bias condition. The top resistive biasing has more benefit with the feature of phase noise than MOS current source since it can support the low-noise characteristics and large output swing. The LC-VCO designed in 130-nm CMOS process with 0.7-V supply voltage achieves phase noise of -116 dBc/Hz at 200 kHz offset with tuning range of 398 MHz to 408 MHz covering medical implant communication service (MICS) band.
文摘This paper introduces a modified design of CMOS dynamic Phase Frequency Detector (PFD). The proposed PFD circuit (PPFD) is designed, simulated and the results obtained are analyzed. In order to reduce dead zone, internal signal routing is used in the PPFD circuit. To extend, Phase Locked Loop (PLL) is designed and it is verified with two different Frequency Divider (FD) circuits. There is a decrease in area of the PPFD circuit with 16 transistors and dissipates power of 40.8 pW for 1.2 V power supply. The pre-layout simulation result shows that the PPFD circuit has an elimination of a dead zone. Further, it works with the high speed and reduced power operated in the reference frequency of 50 MHz and the feedback frequency up to 4 GHz.
