研究了深亚微米pMOS器件的热载流子注入(hot-carrier injection,HCI)和负偏压温度不稳定效应(negative bias temperature instability,NBTI)的耦合效应和物理机制.器件在室温下的损伤特性由HCI效应来控制.高温条件下,器件受到HCI和NBTI...研究了深亚微米pMOS器件的热载流子注入(hot-carrier injection,HCI)和负偏压温度不稳定效应(negative bias temperature instability,NBTI)的耦合效应和物理机制.器件在室温下的损伤特性由HCI效应来控制.高温条件下,器件受到HCI和NBTI效应的共同作用,二者的混合效应表现为NBTI不断增强的HCI效应.在HCI条件下器件的阈值电压漂移依赖沟道长度,而NBTI效应中器件的阈值电压漂移与沟道长度无关,给出了分解HCI和NBTI耦合效应的方法.展开更多
通过理论分析与计算机模拟 ,给出了以提高跨导为目标的 Si/ Si Ge PMOSFET优化设计方法 ,包括栅材料的选择、沟道层中 Ge组分及其分布曲线的确定、栅氧化层及 Si盖帽层厚度的优化和阈值电压的调节 ,基于此已研制出 Si/ Si Ge PMOSFET器...通过理论分析与计算机模拟 ,给出了以提高跨导为目标的 Si/ Si Ge PMOSFET优化设计方法 ,包括栅材料的选择、沟道层中 Ge组分及其分布曲线的确定、栅氧化层及 Si盖帽层厚度的优化和阈值电压的调节 ,基于此已研制出 Si/ Si Ge PMOSFET器件样品 .测试结果表明 ,当沟道长度为 2μm时 ,Si/ Si Ge PMOS器件的跨导为 45 m S/ mm(30 0 K)和 92 m S/ mm (77K) ,而相同结构的全硅器件跨导则为 33m S/ mm (30 0 K)和 39m S/ m m (77K) .展开更多
应用负偏置温度不稳定性(negative bias temperature instability,NBTI),退化氢分子的漂移扩散模型,与器件二维数值模拟软件结合在一起进行计算,并利用已有的实验数据和基本器件物理和规律,分析直流应力NBTI效应随器件沟道长度、栅氧层...应用负偏置温度不稳定性(negative bias temperature instability,NBTI),退化氢分子的漂移扩散模型,与器件二维数值模拟软件结合在一起进行计算,并利用已有的实验数据和基本器件物理和规律,分析直流应力NBTI效应随器件沟道长度、栅氧层厚度和掺杂浓度等基本参数的变化规律,是研究NBTI可靠性问题发生和发展机理变化的一种有效方法.分析结果显示,NBTI效应不受器件沟道长度变化的影响,而主要受到栅氧化层厚度变化的影响;栅氧化层厚度的减薄和栅氧化层电场增强的影响是一致的,决定了器件退化按指数规律变化;当沟道掺杂浓度提高,NBTI效应将减弱,这是因为器件沟道表面空穴浓度降低引起的;然而当掺杂浓度提高到器件的源漏泄漏电流很小时(小泄露电流器件),NBTI效应有明显的增强.这些结论对认识NBTI效应的发展规律以及对高性能器件的设计具有重要的指导意义.展开更多
研究了热载流子应力下栅厚为 2 .1nm ,栅长为 0 .135μm的 p MOSFET中 HAL O掺杂剂量与器件的退化机制和参数退化的关系 .实验发现 ,器件的退化机制对 HAL O掺杂剂量的改变不敏感 ,但是器件的线性漏电流、饱和漏电流、最大跨导的退化随...研究了热载流子应力下栅厚为 2 .1nm ,栅长为 0 .135μm的 p MOSFET中 HAL O掺杂剂量与器件的退化机制和参数退化的关系 .实验发现 ,器件的退化机制对 HAL O掺杂剂量的改变不敏感 ,但是器件的线性漏电流、饱和漏电流、最大跨导的退化随着 HAL O掺杂剂量的增加而增加 .实验同时发现 ,器件参数的退化不仅与载流子迁移率的退化、漏串联电阻增大有关 ,而且与阈值电压的退化和应力前阈值电压有关 .展开更多
A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET.Experimental results were used to validate this model.Th...A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET.Experimental results were used to validate this model.The extracted parameters from our model were tOX=20 nm,ND=1×1016cm 3,tSSi=13.2 nm,consistent with the experimental values.The results show that the simulation results agree with experimental data well.It is found that the plateau can be strongly affected by doping concentration,strained-Si layer thickness and mass fraction of Ge in the SiGe layer.The model has been implemented in the software for strained silicon MOSFET parameter extraction,and has great value in the design of the strained-Si/SiGe devices.展开更多
Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si 1-x Ge x /relaxd Si 1-y Ge y (s-Si/s-SiGe/Si 1-y Ge y) metal-oxide-semiconductor field-effect tr...Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si 1-x Ge x /relaxd Si 1-y Ge y (s-Si/s-SiGe/Si 1-y Ge y) metal-oxide-semiconductor field-effect transistor (PMOSFET),an-alytical expressions of the threshold voltages for buried channel and surface channel are presented.And the maximum allowed thickness of s-Si is given,which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si),because the hole mobility in the buried channel is higher than that in the surface channel.Thus they offer a good accuracy as compared with the results of device simulator ISE.With this model,the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted,such as Ge fraction,layer thickness,and doping concentration.This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si 1-y Ge y metal-oxide-semiconductor field-effect transistor (MOSFET) designs.展开更多
The hot carrier effect (HCE) of an ultra-deep sub-micron p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) is investigated in this paper. Experiments indicate that the generation of positively char...The hot carrier effect (HCE) of an ultra-deep sub-micron p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time (t), channel width (W ), channel length (L), and stress voltage (Vd ) is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly.展开更多
文摘研究了深亚微米pMOS器件的热载流子注入(hot-carrier injection,HCI)和负偏压温度不稳定效应(negative bias temperature instability,NBTI)的耦合效应和物理机制.器件在室温下的损伤特性由HCI效应来控制.高温条件下,器件受到HCI和NBTI效应的共同作用,二者的混合效应表现为NBTI不断增强的HCI效应.在HCI条件下器件的阈值电压漂移依赖沟道长度,而NBTI效应中器件的阈值电压漂移与沟道长度无关,给出了分解HCI和NBTI耦合效应的方法.
文摘通过理论分析与计算机模拟 ,给出了以提高跨导为目标的 Si/ Si Ge PMOSFET优化设计方法 ,包括栅材料的选择、沟道层中 Ge组分及其分布曲线的确定、栅氧化层及 Si盖帽层厚度的优化和阈值电压的调节 ,基于此已研制出 Si/ Si Ge PMOSFET器件样品 .测试结果表明 ,当沟道长度为 2μm时 ,Si/ Si Ge PMOS器件的跨导为 45 m S/ mm(30 0 K)和 92 m S/ mm (77K) ,而相同结构的全硅器件跨导则为 33m S/ mm (30 0 K)和 39m S/ m m (77K) .
文摘应用负偏置温度不稳定性(negative bias temperature instability,NBTI),退化氢分子的漂移扩散模型,与器件二维数值模拟软件结合在一起进行计算,并利用已有的实验数据和基本器件物理和规律,分析直流应力NBTI效应随器件沟道长度、栅氧层厚度和掺杂浓度等基本参数的变化规律,是研究NBTI可靠性问题发生和发展机理变化的一种有效方法.分析结果显示,NBTI效应不受器件沟道长度变化的影响,而主要受到栅氧化层厚度变化的影响;栅氧化层厚度的减薄和栅氧化层电场增强的影响是一致的,决定了器件退化按指数规律变化;当沟道掺杂浓度提高,NBTI效应将减弱,这是因为器件沟道表面空穴浓度降低引起的;然而当掺杂浓度提高到器件的源漏泄漏电流很小时(小泄露电流器件),NBTI效应有明显的增强.这些结论对认识NBTI效应的发展规律以及对高性能器件的设计具有重要的指导意义.
基金Projects(51308040203,6139801)supported by National Ministries and Commissions,ChinaProjects(72105499,72104089)supported by the Fundamental Research Funds for the Central Universities,ChinaProject(2010JQ8008)supported by the Natural Science Basic Research Plan in Shaanxi Province of China
文摘A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET.Experimental results were used to validate this model.The extracted parameters from our model were tOX=20 nm,ND=1×1016cm 3,tSSi=13.2 nm,consistent with the experimental values.The results show that the simulation results agree with experimental data well.It is found that the plateau can be strongly affected by doping concentration,strained-Si layer thickness and mass fraction of Ge in the SiGe layer.The model has been implemented in the software for strained silicon MOSFET parameter extraction,and has great value in the design of the strained-Si/SiGe devices.
基金Project supported by the National Defence Pre-research Foundation of China (Grant Nos. 51308040203,9140A08060407DZ0103,and 6139801)
文摘Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si 1-x Ge x /relaxd Si 1-y Ge y (s-Si/s-SiGe/Si 1-y Ge y) metal-oxide-semiconductor field-effect transistor (PMOSFET),an-alytical expressions of the threshold voltages for buried channel and surface channel are presented.And the maximum allowed thickness of s-Si is given,which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si),because the hole mobility in the buried channel is higher than that in the surface channel.Thus they offer a good accuracy as compared with the results of device simulator ISE.With this model,the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted,such as Ge fraction,layer thickness,and doping concentration.This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si 1-y Ge y metal-oxide-semiconductor field-effect transistor (MOSFET) designs.
基金Project supported by the National Basic Research Program of China (Grant No. 2011CBA00606)the National Natural Science Foundation of China (Grant No. 61106106)the Fundamental Research Funds for the Central Universities, China (Grant No. K50510250006)
文摘The hot carrier effect (HCE) of an ultra-deep sub-micron p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time (t), channel width (W ), channel length (L), and stress voltage (Vd ) is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly.
