We fabricate p-channel metal-oxide-semiconductor-field-effect-transistors(PMOSFETs)with a HfSiAlON/MoAlN gate stack using a novel and practical gate-last process.In the process,SiO_(2)/poly-Si is adopted as the dummy ...We fabricate p-channel metal-oxide-semiconductor-field-effect-transistors(PMOSFETs)with a HfSiAlON/MoAlN gate stack using a novel and practical gate-last process.In the process,SiO_(2)/poly-Si is adopted as the dummy gate stack and replaced by an HfSiAlON/MoAlN gate stack after source/drain formation.Because of the high-k/metal-gate stack formation after the 1000℃source/drain ion-implant doping activation,the fabricated PMOSFET has good electrical characteristics.The device's saturation driving current is 2.71×10^(-4) A/μm(VGS=VDS=-1.5 V)and the off-state current is 2.78×10^(-9) A/μm.The subthreshold slope of 105 mV/dec(VDS=-1.5 V),drain induced barrier lowering of 80 mV/V and Vth of -0.3 V are obtained.The research indicates that the present PMOSFET could be a solution for high performance PMOSFET applications.展开更多
Hot carrier injection （HCI） at high temperatures and different values of gate bias Vg has been performed in order to study the actions of negative bias temperature instability （NBTI） and hot carriers. Hot-carrier-...Hot carrier injection （HCI） at high temperatures and different values of gate bias Vg has been performed in order to study the actions of negative bias temperature instability （NBTI） and hot carriers. Hot-carrier-stress-induced damage at Vg = Vd, where Vd is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different： the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）. We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.展开更多
Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all de...Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.展开更多
Based on theoretical analysis and computer-aided simulation, optimized design principles for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials,determination of germanium percentage and pr...Based on theoretical analysis and computer-aided simulation, optimized design principles for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials,determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage. In the light of these principles,a SiGe PMOSFET is designed and fabricated successfully. Measurement indicates that the SiGe PMOSFET's (L=2μm) transconductance is 45 mS/mm (300K) and 92mS/mm (77K), while that is 33 mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.展开更多
A physical model of hole mobility for germanium-on-insulator p MOSFETs is built by analyzing all kinds of scattering mechanisms, and a good agreement of the simulated results with the experimental data is achieved, co...A physical model of hole mobility for germanium-on-insulator p MOSFETs is built by analyzing all kinds of scattering mechanisms, and a good agreement of the simulated results with the experimental data is achieved, confirming the validity of this model. The scattering mechanisms involved in this model include acoustic phonon scattering, ionized impurity scattering, surface roughness scattering, coulomb scattering and the scattering caused by Ge film thickness fluctuation. The simulated results show that the coulomb scattering from the interface charges is responsible for the hole mobility degradation in the low-field regime and the surface roughness scattering limits the hole mobility in the high-field regime. In addition, the effects of some factors, e.g. temperature, doping concentration of the channel and the thickness of Ge film, on degradation of the mobility are also discussed using the model, thus obtaining a reasonable range of the relevant parameters.展开更多
Extremely thin silicon on insulator p-channel metal oxide-semiconductor field-effect transistors （PMOSFETs） with implanted doping and in situ doping are analyzed by TCAD simulation. The critical characteris- tic par...Extremely thin silicon on insulator p-channel metal oxide-semiconductor field-effect transistors （PMOSFETs） with implanted doping and in situ doping are analyzed by TCAD simulation. The critical characteris- tic parameters acquired by TCAD simulation are compared with each other to analyze their electrical perfbrmance. The saturated driven currents of implanted doping devices with a 25 nm gate length （Lg） are about 200 ×μA/μm bigger than the in situ doping devices at the same saturated threshold voltage （Vtsat）. Meanwhile the drain-induced barrier lowering （DIBL） and saturated subthreshold swings for implanted doping devices are also 30 50 mV/V and 6.3-9.1 mV/dec smaller than those of in situ doping devices at 25 nm Lg and a 9-11 nm thickness of SOl （Tsi）, respectively. The shift of Vtsat with Tsi for in situ doping devices with 15 nm Lg is -31.8 mV/nm, whereas that for in situ doping devices is only -6.8 mV/nm. These outcomes indicate that the devices with implanted doping can produce a more advanced and stable electrical performance.展开更多
The total dose radiation and annealing responses of the back transistor of Silicon-On-Insulator （SOI） pMOSFETs have been studied by comparing them with those of the back transistor of SOI nMOSFETs fabricated on the ...The total dose radiation and annealing responses of the back transistor of Silicon-On-Insulator （SOI） pMOSFETs have been studied by comparing them with those of the back transistor of SOI nMOSFETs fabricated on the same wafer. The transistors were irradiated by 60Co γ-rays with various doses and the front transistors were biased in a Float-State and Off-State, respectively, during irradiation. The total dose radiation responses of the back transistors were characterized by their threshold voltage shifts. The results show that the total dose radiation response of the back transistor of SOI pMOSFETs, similar to that of SOI nMOSFETs, depends greatly on their bias conditions during irradiation. However, with the Float-State bias rather than the Off-State bias, the back transistors of SOI pMOSFETs reveal a much higher sensitivity to total dose radiation, which is contrary to the behavior of SOI nMOSFETs. In addition, it is also found that the total dose radiation effect of the back transistor of SOI pMOSFETs irradiated with Off-State bias, as well as that of the SOI nMOSFETs, increases as the channel length decreases. The annealing response of the back transistors after irradiation at room temperature without bias, as characterized by their threshold voltage shifts, indicates that there is a relatively complex annealing mechanism associated with channel length, type, and bias condition during irradiation. In particular, for all of the transistors irradiated with Off-State bias, their back transistors show an abnormal annealing effect during early annealing. All of these results have been discussed and analyzed in detail by the aid of simulation.展开更多
基金Supported by the Beijing Natural Science Foundation under Grant No 4123106the Important National Science&Technology Specific Projects of China under Grant No 2009ZX02035.
文摘We fabricate p-channel metal-oxide-semiconductor-field-effect-transistors(PMOSFETs)with a HfSiAlON/MoAlN gate stack using a novel and practical gate-last process.In the process,SiO_(2)/poly-Si is adopted as the dummy gate stack and replaced by an HfSiAlON/MoAlN gate stack after source/drain formation.Because of the high-k/metal-gate stack formation after the 1000℃source/drain ion-implant doping activation,the fabricated PMOSFET has good electrical characteristics.The device's saturation driving current is 2.71×10^(-4) A/μm(VGS=VDS=-1.5 V)and the off-state current is 2.78×10^(-9) A/μm.The subthreshold slope of 105 mV/dec(VDS=-1.5 V),drain induced barrier lowering of 80 mV/V and Vth of -0.3 V are obtained.The research indicates that the present PMOSFET could be a solution for high performance PMOSFET applications.
基金Project supported by the National Natural Science Foundation of China （Grant No 60206006）. the Program for New Century Excellent Talents of Ministry of Education of China （Grant No 681231366）. the National Defense Pre-Research Foundation of China （Grant No 51408010305DZ0168） and the Key Project of Chinese Ministry of Education （Grant No 104172）.
文摘Hot carrier injection （HCI） at high temperatures and different values of gate bias Vg has been performed in order to study the actions of negative bias temperature instability （NBTI） and hot carriers. Hot-carrier-stress-induced damage at Vg = Vd, where Vd is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different： the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）. We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.
基金Project supported by the National Natural Science Foundation of China （Grant No 60206006）, the Program for New Century Excellent Talents of Ministry of Education of China （Grant No 681231366）, the National Defense Pre-Research Foundation of China （Grant No 51308040103） and the Key Project of Chinese Ministry of Education （Grant No 104172）.
文摘Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.
基金Supported by National Key Laboratory Fund (99Js09 5.1)
文摘Based on theoretical analysis and computer-aided simulation, optimized design principles for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials,determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage. In the light of these principles,a SiGe PMOSFET is designed and fabricated successfully. Measurement indicates that the SiGe PMOSFET's (L=2μm) transconductance is 45 mS/mm (300K) and 92mS/mm (77K), while that is 33 mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.
基金Project supported by the National Natural Science Foundation of China(Nos.61274112,61176100,61404055)
文摘A physical model of hole mobility for germanium-on-insulator p MOSFETs is built by analyzing all kinds of scattering mechanisms, and a good agreement of the simulated results with the experimental data is achieved, confirming the validity of this model. The scattering mechanisms involved in this model include acoustic phonon scattering, ionized impurity scattering, surface roughness scattering, coulomb scattering and the scattering caused by Ge film thickness fluctuation. The simulated results show that the coulomb scattering from the interface charges is responsible for the hole mobility degradation in the low-field regime and the surface roughness scattering limits the hole mobility in the high-field regime. In addition, the effects of some factors, e.g. temperature, doping concentration of the channel and the thickness of Ge film, on degradation of the mobility are also discussed using the model, thus obtaining a reasonable range of the relevant parameters.
基金supported by the Institute of Microelectronics,Chinese Academy of Sciences
文摘Extremely thin silicon on insulator p-channel metal oxide-semiconductor field-effect transistors （PMOSFETs） with implanted doping and in situ doping are analyzed by TCAD simulation. The critical characteris- tic parameters acquired by TCAD simulation are compared with each other to analyze their electrical perfbrmance. The saturated driven currents of implanted doping devices with a 25 nm gate length （Lg） are about 200 ×μA/μm bigger than the in situ doping devices at the same saturated threshold voltage （Vtsat）. Meanwhile the drain-induced barrier lowering （DIBL） and saturated subthreshold swings for implanted doping devices are also 30 50 mV/V and 6.3-9.1 mV/dec smaller than those of in situ doping devices at 25 nm Lg and a 9-11 nm thickness of SOl （Tsi）, respectively. The shift of Vtsat with Tsi for in situ doping devices with 15 nm Lg is -31.8 mV/nm, whereas that for in situ doping devices is only -6.8 mV/nm. These outcomes indicate that the devices with implanted doping can produce a more advanced and stable electrical performance.
基金Supported by National Natural Science Foundation of China(61404169)
文摘The total dose radiation and annealing responses of the back transistor of Silicon-On-Insulator （SOI） pMOSFETs have been studied by comparing them with those of the back transistor of SOI nMOSFETs fabricated on the same wafer. The transistors were irradiated by 60Co γ-rays with various doses and the front transistors were biased in a Float-State and Off-State, respectively, during irradiation. The total dose radiation responses of the back transistors were characterized by their threshold voltage shifts. The results show that the total dose radiation response of the back transistor of SOI pMOSFETs, similar to that of SOI nMOSFETs, depends greatly on their bias conditions during irradiation. However, with the Float-State bias rather than the Off-State bias, the back transistors of SOI pMOSFETs reveal a much higher sensitivity to total dose radiation, which is contrary to the behavior of SOI nMOSFETs. In addition, it is also found that the total dose radiation effect of the back transistor of SOI pMOSFETs irradiated with Off-State bias, as well as that of the SOI nMOSFETs, increases as the channel length decreases. The annealing response of the back transistors after irradiation at room temperature without bias, as characterized by their threshold voltage shifts, indicates that there is a relatively complex annealing mechanism associated with channel length, type, and bias condition during irradiation. In particular, for all of the transistors irradiated with Off-State bias, their back transistors show an abnormal annealing effect during early annealing. All of these results have been discussed and analyzed in detail by the aid of simulation.
