Step memory polynomial predistorter for power amplifiers with memory

To reduce the number of digital predistortion coefficients, a step memory polynomial （SMP）predistorter is presented. The number of predistortion coefficients is decreased by adjusting the maximum nonlinear order for different memory orders in the traditional memory polynomial （MP）predistorter. The proposed SNIP predistorter is identified by an offline learning structure on which the coefficients can be extracted directly from the sampled input and output of a PA. Simulation results show that the SMP predistorter is not tied to a particular PA model and is, therefore, robust. The effectiveness of the SMP predistorter is demonstrated by simulations and experiments on an MP model, a parallel Wiener model, a Wiener-Hammerstein model, a sparsedelay memory polynomial model and a real PA which is fabricated based on the Freescale LDMOSFET MRF21030. Compared with the traditional MP predistorter, the SMP predistorter can reduce the number of coefficients by 60%.

Design of a memory polynomial predistorter for wideband envelope tracking amplifiers

Efficiency and linearity of the microwave power amplifier are critical elements for mobile communication systems. A memory polynomial baseband predistorter based on an indirect learning architecture is presented for improving the linearity of an envelope tracing （ET） amplifier with application to a wireless transmitter. To deal with large peak-to-average ratio （PAR） problem, a clipping procedure for the input signal is employed. Then the system performance is verified by simulation results. For a single carrier wideband code division multiple access （WCDMA） signal of 16-quadrature amplitude modulation （16-QAM）, about 2% improvement of the error vector magnitude （EVM） is achieved at an average output power of 45.5 dBm and gain of 10.6 dB, with adjacent channel leakage ratio （ACLR） of -64.55 dBc at offset frequency of 5 MHz. Moreover, a three-carrier WCDMA signal and a third-generation （3G） long term evolution （LTE） signal are used as test signals to demonstrate the performance of the proposed linearization scheme under different bandwidth signals.

Realization of a tunable analog predistorter using parallel combination technique for laser driver applications

This paper describes a new approach for designing analog predistorters that can compensate for the nonlinear distortion of laser drivers in a radio-over-fiber （RoF） system. In contrast to previous works, this paper analyzes the transfer characteristics of CMOS transistors, by combining parallel currents of CMOS transistors in various W/L and negative bias voltages to realize the tunable analog predistortion function. The circuit is fabricated by a standard 0.18txm CMOS technology. The core circuit current consumption is only 15mA and the entire driver circuit works in a band-pass from 1 - 2.2GHz. Experimental results of two-tone tests have shown that with an analog predistortoer the IIP3 of the laser driver circuit has an improvement of 4.91 dB.

Robust power amplifier predistorter by using memory polynomials

In memory polynomial predistorter design, the coefficient estimation algorithm based on normalized least mean square is sensitive to initialization parameters. A predistorter based on generalized normalized gradient descent algorithm is proposed. The merit of the GNGD algorithm is that its learning rate provides compensation for the independent assumptions in the derivation of NLMS, thus its stability is improved. Computer simulation shows that the proposed predistorter is very robust. It can overcome the sensitivity of initialization parameters and get a better linearization performance.

A Discrete Newton's Method for Gain Based Predistorter

Gain based predistorter (PD) is a highly effective and simple digital baseband predistorter which compensates for the nonlinear distortion of PAs. Lookup table (LUT) is the core of the gain based PD. This paper presents a discrete Newton’s method based adaptive technique to modify LUT. We simplify and convert the hardship of adaptive updating LUT to the roots finding problem for a system of two element real equations on athematics. And we deduce discrete Newton’s method based adaptive iterative formula used for updating LUT. The iterative formula of the proposed method is in real number field, but secant method previously published is in complex number field. So the proposed method reduces the number of real multiplications and is implemented with ease by hardware. Furthermore, computer simulation results verify gain based PD using discrete Newton’s method could rectify nonlinear distortion and improve system performance. Also, the simulation results reveal the proposed method reaches to the stable statement in fewer iteration times and less runtime than secant method.

A dynamic coefficient polynomial predistorter based on direct learning architecture

A dynamic coefficient polynomial predistorter based on direct learning architecture is proposed.Compared to the existing polynomial predistorter,on the one hand,the proposed predistorter based on thedirect learning architecture is more robust to initial conditions of the tap coefficients than that based on in-direct learning architecture;on the other hand,by using two polynomial coefficient combinations,differ-ent polynomial coefficient combination can be selected when the input signal amplitude changes,whicheffectively decreases the estimate error.This paper introduces the direct learning architecture and givesthe dynamic coefficient polynomial expression.A simplified nonlinear recursive least-squares(RLS)algo-rithm for polynomial coefficient estimation is also derived in detail.Computer simulations show that theproposed predistorter can attain 31 dB,28dB and 40dB spectrum suppression gain when our method is ap-plied to the traveling wave tube amplifier(TWTA),solid state power amplifier(SSPA)and polynomialpower amplifier(PA)model,respectively.

Adaptive Hammerstein Predistorter Using the Recursive Prediction Error Method

The digital baseband predistorter is an effective technique to compensate for the nonlinearity of power amplifiers （PAs） with memory effects. However, most available adaptive predistorters based on direct learning architectures suffer from slow convergence speeds. In this paper, the recursive prediction error method is used to construct an adaptive Hammerstein predistorter based on the direct learning architecture, which is used to linearize the Wiener PA model. The effectiveness of the scheme is demonstrated on a digital video broadcasting-terrestrial system. Simulation results show that the predistorter outperforms previous predistorters based on direct learning architectures in terms of convergence speed and linearization. A similar algorithm can be applied to estimate the Wiener PA model, which will achieve high model accuracy.

Performance of a recursive algorithm for polynomial predistorter design

In this article, based on least square estimation, a recursive algorithm for indirect learning structure predistorter is introduced. Simulation results show that of all polynomial predistorter nonlinear terms, higher-order （higher than 7th-order） nonlinear terms are so minor that they can be omitted in practical predistorter design. So, it is unnecessary to construct predistorter with higher-order polynomials, and the algorithm will always be stable. Further results show that even when 15th-order polynomial model is used, the algorithm is convergent after 10 iterations, and it can improve out-band spectrum of 20 MHz bandwidth signal by 64 dB, with a 1.2×10^11 matrix condition number.

New predistorter using triangular memory polynomial for power amplifier of OFDM-based wireless broadband communication system

A triangular memory polynomial （TMP） predistorter is presented in this paper to linearize a power amplifier＇s nonlinear with memory effects. Compared with the traditional memory polynomial （MP） predistorter, the coefficients of TMP predistorter is reduced more than 75%, which can effectively decrease the implementation complexity. The coefficients of predistorter are directly extracted from an offline system identification process by an open-loop structure in our approach. Several signals with data rate 5 MHz, 10 MHz, 15 MHz and 20 MHz are used to verify the performance of the proposed predistorter. Experimental results show that the proposed TMP predistorter and the traditional MP predistorter almost have the same performance.

Highly efficient class-F power amplifier with digital predistortion for WCDMA applications

A digital predistorted class-F power amplifier （PA） using Cree GaN HEMT CGH40010 operating at 2. 12 GHz is presented to obtain high efficiency and excellent linearity for wideband code-division multiple access （ WCDMA ） applications. Measurement results with the continuous wave （CW） signals indicate that the designed class-F PA achieves a peak power-added efficiency （PAE） of 75. 2% with an output power of 39.4 dBm. The adjacent channel power ratio （ACPR） of the designed PA after digital predistortion （DPD） decreases from -28. 3 and -27. 5 dBc to -51.9 and -54. 0 dBc, respectively, for a 4-carrier 20 MHz WCDMA signal with 7. 1 dB peak to average power ratio （PAPR）. The drain efficiency （DE） of the PA is 37. 8% at an average output power of 33. 3 dBm. The designed power amplifier can be aoolied in the WCDMA system.

BLOCK CODING SCHEME FOR REDUCING PAPR IN OFDM SYSTEMS WITH LARGE NUMBER OF SUBCARRIERS

The major drawback in Orthogonal Frequency Division Multiplexing (OFDM) system is due to the high Peak-to-Average Power Ratio (PAPR), so the performance of the system is significantly degraded by the nonlinearity of a High Power Amplifier (HPA) in the transmitter.In order to mitigate distortion, a block coding scheme for reducing PAPR in OFDM systems with large number of subcarriers based on complementary sequences and predistortion is proposed,which is capable of both error correction and PAPR reduction. Computer simulation results show that the proposed scheme significantly improves Bit Error Rate(BER) performance as compared to an uncoded system when an HPA is employed or a coded system without predistortion.

Adaptive Digital Predistortion Schemes to Linearize RF Power Amplifiers with Memory Effects

To compensate for nonlinear distortion introduced by RF power amplifiers （PAs） with memory effects, two correlated models, namely an extended memory polynomial （EMP） model and a memory lookup table （LUT） model, are proposed for predistorter design. Two adaptive digital predistortion （ADPD） schemes with indirect learning architecture are presented. One adopts the EMP model and the recursive least square （RLS） algorithm, and the other utilizes the memory LUT model and the least mean square （LMS） algorithm. Simulation results demonstrate that the EMP-based ADPD yields the best linearization performance in terms of suppressing spectral regrowth. It is also shown that the ADPD based on memory LUT makes optimum tradeoff between performance and computational complexity.

ANALOG PREDISTORTION LINEARIZER ON REDUCING CORRECTED AMPLITUDE OVERSHOOT

This paper presents a dual-nonlinear branch linearizer for reducing the corrected amplitude overshoot of conventional single nonlinear branch linearizer. Theoretical analysis is carried out, the analysis is verified by simulation, and a prototype of Ka band 25.28~26.08 GHz dual nonlinear branch linearizer is achieved. It indicates that the corrected amplitude overshoot is less than 0.5 dB, the C/I3 improvement is more than 10 dB related to a single carrier IBO 9 dB, when it is linked and tested for 50 W spacebrone Travelling Wave Tube Amplifier(TWTA).

Wavelet network based predistortion method for wideband RF power amplifiers exhibiting memory effects

RF power amplifiers (PAs) are usually considered as memoryless devices in most existing predistortion techniques. Nevertheless, in wideband communication systems, PA memory effects can no longer be ignored and memoryless predistortion cannot linearize PAs effectively. After analyzing PA memory effects, a novel predistortion method based on wavelet networks (WNs) is proposed to linearize wideband RF power amplifiers. A complex wavelet network with tapped delay lines is applied to construct the predistorter and then a complex backpropagation algorithm is developed to train the predistorter parameters. The simulation results show that compared with the previously published feed-forward neural network predistortion method, the proposed method provides faster convergence rate and better performance in reducing out-of-band spectral regrowth.

Robust Digital Predistortion for LTE/5G Power Amplifiers Utilizing Negative Feedback Iteration

A robust digital predistortion(DPD)technique utilizing negative feedback iteration is introduced for linearizing power amplifiers(PAs)in long term evolution(LTE)/5G systems.Different from the conventional direct learning and indirect learning structure,the proposed DPD suggests a two-step method to identify the predistortion.Firstly,a negative feedback based iteration is used to estimate the optimal DPD signal.Then the corresponding DPD parameters are extracted by forward modeling with the input signal and optimal DPD signal.The iteration can be applied to both single-band and dual-band PAs,which will achieve superior linear performance than the conventional direct learning DPD while having a relatively low computational complexity.The measurement is carried out on a broadband Doherty PA(DPA)with a 200 MHz bandwidth LTE signal at 2.1 GHz,and on a 5G DPA with two 10 MHz LTE signals at 3.4/3.6 GHz for validation in dual-band scenarios.

Digital Predistortion and Measurement Method

Digital PreDistortion(DPD)is a very useful method to improve the linearity of Power Amplifiers(PAs)for LTE and upcoming 5 G networks.As the spectrum resources are becoming more and more crowded,and the communications bandwidth are broader,the ACPR(Adjacent Channel Leakage Ratio)is very important to communication systems.DPD is one of the useful means for PA to reduce ACPR.This article demonstrates what DPD is and how DPD is achieved,the measurement of the Digital Distortion of a PA using a vector generator and vector analyzer,and the measurement results has been discussed.

Volterra series based predistortion for broadband RF power amplifiers with memory effects

RF power amplifiers （PAs） are usually considered as memoryless devices in most existing predistortion techniques. However, in broadband communication systems, such as WCDMA, the PA memory effects are significant, and memoryless predistortion cannot linearize the PAs effectively. After analyzing the PA memory effects, a novel predistortion method based on the simplified Volterra series is proposed to linearize broadband RF PAs with memory effects. The indirect learning architecture is adopted to design the predistortion scheme and the reeursive least squares algorithm with forgetting factor is applied to identify the parameters of the predistorter. Simulation results show that the proposed predistortion method can compensate the nonlinear distortion and memory effects of broadband RF PAs effectively.

Non-Overlapping Conditions to Enable Multi- Dimensional Behavioral Models/DPDs for Multi-Band or Non-Continuous Carrier Aggregation Systems

To linearize the multi.band PAs/transmitters, a serial of multi.band predistortion models based on multi.dimensional architecture have been proposed. However, most of these models work properly only for the signals whose harmonic and intermodulation products of carriers' non.overlap with the interested fundamental bands. In this paper, the non.overlapping conditions for dual.band and tri.band signals are derived and denoted in the form of closed.form expression. It can be used to verify whether a given dual.band/multi.band signals can be linearized properly by these multi.dimensional behavioral models. Also the conditions can be used to plan the frequency spacing and maximum bandwidth of a multi.band or non.continuous carrier aggregation signal. Several dual.band and triband signals were tested on the same PA, by employing 2.D DPD and 3.D DPD behavioral models. The measurement results show that the signals which don't satisfy the non.overlapping conditions cannot be linearized well by the multi.dimensional behavioral models which does not take the harmonic and intermodulation products of carriers' into account.

A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System

At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency （RF） power amplifier system is reducing its complexity of engineering realization and improving anti-jamming ability and computational speed. Besides, opening up its application scope should be contained. For these targets, a novel method including integer loop delay estimation and fractional part is proposed. The integer part applies amplitude-difference summation function and the fractional one adopts the method of finite impulse response （FIR） linear interpolation. The algorithm finds wide applications. What is more, strong anti-jamming ability and low complexity are also its merits. Simulation results support the above opinion. Digital predistortion （DPD） system based on this algorithm achieves good performance.

FPGA Implementation of a Power Amplifier Linearizer for an ETSI-SDR OFDM Transmitter

Most satellite digital radio （SDR） systems use orthogonal frequency-division multiplexing （OFDM） transmission, which means that variable envelope signals are distorted by the RF power amplifier （PA）. It is customary to back off the input power to the PA to avoid the PA nonlinear region of operation. In this way, linearity can be achieved at the cost of power efficiency. Another attractive option is to use a linearizer, which compensates for the nonlinear effects of the PA. In this paper, an OFDM transmitter conforming to European Telecommunications Standard Institute SDR Technical Specifications 2007-2008 was designed and implemented on a low-cost field-programmable gate array （FPGA） platform. A weakly nonlinear PA, operating in the L-band SDR frequency, was used for signal transmission. An adaptive linearizer was designed and implemented on the same FPGA device using digital predistortion to correct the undesired effects of the PA on the transmitted signal. Test results show that spectral distortion can be suppressed between 6-9 dB using the designed linearizer when the PA is driven close to its saturation region.