By analyzing the principle of process variations, a lightweight Physical Unclonable Function （PUF） circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inv...By analyzing the principle of process variations, a lightweight Physical Unclonable Function （PUF） circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation （SMIC） 65 nm CMOS technology and the layout area is 2.94μm × 1.68μm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.展开更多
针对低成本无线射频识别(RFID)系统存在的安全性问题,提出一种基于PUF的低成本RFID安全协议。利用PUF的物理不可克隆性识别标签的身份,并利用线性反馈移位寄存器(LFSR)产生随机系列,加密阅读器与标签之间的通信,能抵抗重放攻击、跟踪攻...针对低成本无线射频识别(RFID)系统存在的安全性问题,提出一种基于PUF的低成本RFID安全协议。利用PUF的物理不可克隆性识别标签的身份,并利用线性反馈移位寄存器(LFSR)产生随机系列,加密阅读器与标签之间的通信,能抵抗重放攻击、跟踪攻击、物理攻击、窃听攻击等多种攻击。在Altera DE2板上使用FPGA实现PUF和LFSR,采用Quartus II 8.0编程。实验结果证明,该协议的执行时间和门电路数量能达到低成本标签的要求。展开更多
基金Supported by the National Natural Science Foundation of China(Nos.61474068,61404076,61274132)the Zhejiang Provincial Natural Science Foundation of China(No.LQ14F040001)the Doctoral Program of Higher Education of China(No.20113305110005)
文摘By analyzing the principle of process variations, a lightweight Physical Unclonable Function （PUF） circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation （SMIC） 65 nm CMOS technology and the layout area is 2.94μm × 1.68μm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.
文摘针对低成本无线射频识别(RFID)系统存在的安全性问题,提出一种基于PUF的低成本RFID安全协议。利用PUF的物理不可克隆性识别标签的身份,并利用线性反馈移位寄存器(LFSR)产生随机系列,加密阅读器与标签之间的通信,能抵抗重放攻击、跟踪攻击、物理攻击、窃听攻击等多种攻击。在Altera DE2板上使用FPGA实现PUF和LFSR,采用Quartus II 8.0编程。实验结果证明,该协议的执行时间和门电路数量能达到低成本标签的要求。
