Tomasulo algorithm, a dynamic scheduling technique designed for float point unit(FPU) to exploit instruction level parallelism for single thread only is improved into T Tomasulo algorithm to support multiple parallel...Tomasulo algorithm, a dynamic scheduling technique designed for float point unit(FPU) to exploit instruction level parallelism for single thread only is improved into T Tomasulo algorithm to support multiple parallel contexts. FPUs can exploit the parallelisms both within single thread and among multiple threads, and FPUs can be used more effieiently.展开更多
High-performance network processors are expected to play an important role in future high-speed routers. This paper focuses on two representative techniques needed for high-performance network processors: hardwired lo...High-performance network processors are expected to play an important role in future high-speed routers. This paper focuses on two representative techniques needed for high-performance network processors: hardwired logic design and multithread design. Using hardwired logic, this paper compares a single-thread design with a multithread design, and proposes general models and principles to analyze the clock frequency and the resource cost for these environments. Then, two IP header processing schemes, one in single-thread mode and the other in double-thread mode, are developed using these principles and the implementation results verified the theoretical calculation.展开更多
文摘Tomasulo algorithm, a dynamic scheduling technique designed for float point unit(FPU) to exploit instruction level parallelism for single thread only is improved into T Tomasulo algorithm to support multiple parallel contexts. FPUs can exploit the parallelisms both within single thread and among multiple threads, and FPUs can be used more effieiently.
基金Supported by the National High-Tech Research and Development (863) Program of China (No. 863-300-01-99) and the National Natural Science Foundation of China (No. 60173009)
文摘High-performance network processors are expected to play an important role in future high-speed routers. This paper focuses on two representative techniques needed for high-performance network processors: hardwired logic design and multithread design. Using hardwired logic, this paper compares a single-thread design with a multithread design, and proposes general models and principles to analyze the clock frequency and the resource cost for these environments. Then, two IP header processing schemes, one in single-thread mode and the other in double-thread mode, are developed using these principles and the implementation results verified the theoretical calculation.
