Instability of parasitic capacitance in T-shape-gate enhancementmode AlGaN/GaN MIS-HEMTs

Parasitic capacitances associated with overhangs of the T-shape-gate enhancement-mode(E-mode)GaN-based power device,were investigated by frequency/voltage-dependent capacitance-voltage and inductive-load switching measurements.The overhang capacitances induce a pinch-off voltage distinguished from that of the E-mode channel capacitance in the gate capacitance and the gatedrain capacitance characteristic curves.Frequency-and voltage-dependent tests confirm the instability caused by the trapping of interface/bulk states in the LPCVD-SiNx passivation dielectric.Circuit-level double pulse measurement also reveals its impact on switching transition for power switching applications.

Simulation and structure optimization of triboelectric nanogenerators considering the effects of parasitic capacitance

Parasitic capacitance is an unavoidable and usually unwanted capacitance that exists in electric circuits, and it is the most important second-order non-ideal effect that must be considered while designing a triboelectric nanogenerator （TENG） because its magnitude is comparable to the magnitude of the TENG capacitance. This paper investigates the structure and performance optimization of TENGs through modeling and simulation, taking the parasitic capacitance into account. Parasitic capacitance is generally found to cause severe performance degradation in TENGs, and its effects on the optimum matching resistance, maximum output power, and structural figures-of-merit （FOMs） of TENGs are thoroughly investigated and discussed. Optimum values of important structural parameters such as the gap and electrode length are determined for the different working modes of TENGs, systematically demonstrating how these optimum structural parameters change as functions of the parasitic capacitance. Additionally, it is demonstrated that the parasitic capacitance can improve the height tolerance of the metal freestanding-mode TENGs. This work provides a theoretical foundation for the structure and performance optimization of TENGs for practical applications and promotes the development of mechanical energy-harvesting techniques.

Complete Parasitic Capacitance Model of Photovoltaic Panel Considering the Rain Water

Common mode current suppression is important to grid-connected photovoltaic(PV)systems and depends strongly on the value of the parasitic capacitance between the PV panel and the ground.Some parasitic capacitance models have been proposed to evaluate the magnitude of the effective parasitic capacitance.However,the proposed model is only for the PV panels under dry and clean environmental conditions.The dependence of rain water on the capacitance is simply described rather than analyzing in detail.Furthermore,the effects of water are addressed quite differently in papers.Thus,this paper gives complete parasitic capacitance model of the PV panel considering the rain water.The effect of the water on the capacitance is systematically investigated through 3D finite element(FE)electromagnetic(EM)simulations and experiments.Accordingly,it is clarified how the water affects the parasitic capacitance and methods of minimization of the capacitance are proposed.

Simplified parasitic capacitance extraction of shield in HVDC converter system with boundary element method

It is critical to build a wide-band circuit model to conduct research on the characteristics of the electromagnetic disturbance source during the localization of high voltage direct current(HVDC)technology.Parasitic capacitance is most essential for modeling the equivalent circuit,so a fast and accurate computation of capacitance parameters plays a vital role.Because of the large size and complex structure of the converter equipment,it is impossible to obtain capacitance parameters by means of measurement or simulating calculation with finite element software.In this paper,a simplified method of capacitance extraction based on boundary element method is proposed,which can provide an efficient means of establishing simulation models.In the method presented,simulation model of the shield may not be chamfered.Consequently,the edge and corner of the shield do not need to be handled with a sphere,cylinder and other curved surface model.The availability of this method is demonstrated by comparing the capacitance parameters of chamfered shield with that of non-chamfered shield.

Low-parasitic ESD protection strategy for RF ICs in 0.35μm CMOS process

A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge （ESD） protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35μm 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.

Analytical capacitance model for 14 nm Fin FET considering dual-k spacer

The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor（Fin FET） device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the Fin FET device with dual-k spacers.

Parasitic effects of air-gap through-silicon vias in high-speed three-dimensional integrated circuits

In this paper,ground-signal-ground type through-silicon vias（TSVs） exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-circuit model and passive elements（RLGC） parameters based on the physical parameters are presented with the frequency up to 100 GHz.The parasitic capacitance of TSVs can be approximated as the dielectric capacitance of air gaps when the thickness of air gaps is greater than 0.75 μm.Therefore,the applied voltage of TSVs only needs to achieve the flatband voltage,and there is no need to indicate the threshold voltage.This is due to the small permittivity of air gaps.The proposed model shows good agreement with the simulation results of ADS and Ansoft＇s HFSS over a wide frequency range.

Analysis of Light Load Efficiency Characteristics of a Dual Active Bridge Converter Using Wide Band-Gap Devices

In this paper, the zero voltage switching (ZVS) region of a dual active bridge (DAB) converter with wide band-gap (WBG) power semiconductor device is analyzed. The ZVS region of a DAB converter varies depending on output power and voltage ratio. The DAB converters operate with hard switching at light loads, it is difficult to achieve high efficiency. Fortunately, WBG power semiconductor devices have excellent hard switching characteristics and can increase efficiency compared to silicon (Si) devices. In particular, WBG devices can achieve ZVS at low load currents due to their low parasitic output capacitance (Co,tr) characteristics. Therefore, in this paper, the ZVS operating resion is analyzed based on the characteristics of Si, silicon carbide (SiC) and gallium nitride (GaN). Power semiconductor devices. WBG devices with low Co,tr operate at ZVS at lower load currents compared to Si devices. To verify this, experiments are conducted and the results are analyzed using a 3 kW DAB converter. For Si devices, ZVS is achieved above 1.4 kW. For WBG devices, ZVS is achieved at 700 W. Due to the ZVS conditions depending on the switching device, the DAB converter using Si devices achieves a power conversion efficiency of 91% at 1.1 kW output. On the other hand, in the case of WBG devices, power conversion efficiency of more than 98% is achieved under 11 kW conditions. In conclusion, it is confirmed that the WBG device operates in ZVS at a lower load compared to the Si device, which is advantageous in increasing light load efficiency.

Influences of increasing gate stem height on DC and RF performances of InAlAs/InGaAs InP-based HEMTs

The T-gate stem height of In Al As/In Ga As In P-based high electron mobility transistor(HEMT) is increased from165 nm to 250 nm. The influences of increasing the gate stem height on the direct current(DC) and radio frequency(RF)performances of device are investigated. A 120-nm-long gate, 250-nm-high gate stem device exhibits a higher threshold voltage(Vth) of 60 m V than a 120-nm-long gate devices with a short gate stem, caused by more Pt distributions on the gate foot edges of the high Ti/Pt/Au gate. The Pt distribution in Schottky contact metal is found to increase with the gate stem height or the gate length increasing, and thus enhancing the Schottky barrier height and expanding the gate length,which can be due to the increased internal tensile stress of Pt. The more Pt distributions for the high gate stem device also lead to more obvious Pt sinking, which reduces the distance between the gate and the In Ga As channel so that the transconductance(gm) of the high gate stem device is 70 m S/mm larger than that of the short stem device. As for the RF performances,the gate extrinsic parasitic capacitance decreases and the intrinsic transconductance increases after the gate stem height has been increased, so the RF performances of device are obviously improved. The high gate stem device yields a maximum ft of 270 GHz and fmax of 460 GHz, while the short gate stem device has a maximum ft of 240 GHz and the fmax of 370 GHz.

FinFET Performance Enhancement by Source/Drain Cavity Structure Optimization

Fin field-effect transistor(FinFET)technology has been introduced to the mainstream complementary metal-oxide semiconductor(CMOS)manufacturing for low-power and highperformance applications.However,advanced FinFET nodes are facing significant challenges to enhance the device performance due to the increasingly prominent parasitic resistance and capacitance.In this study,for the first time,we demonstrate methods of enhancing p-channel FinFET(pFET)performance on a fully integrated advanced FinFET platform via source/drain(S/D)cavity structure optimization.By modulating the cavity depth and proximity around the optimal reference point,we show that the trade-off between the S/D resistance and short channel effect,as well as the impact on the parasitic capacitance must be considered for the S/D cavity structure optimization.An extra process knob of applying cavity implant on the desired cavity structure was also demonstrated to modify the S/D junction profile for device performance enhancement.

Analysis of Capacitive Parasitism in PWM Inverter-Fed Motor

The effects of parasitic capacitance in induction motor system are unnoticed when it is fed from the AC line, but they are obvious when supplied directly from a PWM inverter. Consequently, many parasitic problems occur, such as motor to earth leakage current, bearing current, incoming line current distortion and uneven distribution of electrical stresses along the winding. On the basis of the uniform transmission line principle, a complete equivalent circuit of the PWM inverter fed motor system is presented, based on which all the capacitive parasitic problems mentioned above are analyzed and simulated by means of PSPICE. All the results are consistent with the existing ones.

New Multipole Method for 3-D Capacitance Extraction

This paper describes an efficient improvement of the multipole accelerated boundary element method for 3-D capacitance extraction. The overall relations between the positions of 2-D boundary elements are considered instead of only the relations between the center-points of the elements, and a new method of cube partitioning is introduced. Numerical results are presented to demonstrate that the method is accurate and has nearly linear computational growth as O(n), where n is the number of panels/boundary elements. The proposed method is more accurate and much faster than Fastcap.

Whole-Chip ESD Protection Design for RF and AMS ICs

As integrated circuits （IC） technologies advance into very-deep-sub-micron （VDSM）, electrostatic discharge （ESD） failure becomes one of the most devastating IC reliability problems and on-chip ESD protection design emerges as a major challenge to radio frequency （RF）, analog, and mixed-signal （AMS） IC designs. This paper reviews key design aspects and recent advances in whole-chip ESD protection designs for RF/AMS IC applications in CMOS technologies.

Two-port Equivalent Circuit Model for UHVDC Converter Valves

UHVDC converter valves during operation may experience overvoltage,which come from the AC or DC systems to which they are connected.Therefore,building an equivalent circuit model(ECM)for the converter valve to analyze the interlayer transient voltage distribution characteristics has important engineering significance for safe and reasonable voltage equalization methods and improving the stability of the DC system.This paper proposes a two-port equivalent circuit model for ±1100 kV converter valve based on the structure of the valve and parameter extraction methods presented.In terms of lumped parameters,integrated ECMs for valve layers are built through impedance-frequency characteristic analysis;in terms of parasitic capacitance parameters,port equivalent parasitic capacitance parameters are obtained by terminal capacitance method and iterative equivalence methods proposed in this paper.By combining integrated ECMs of valve layers and port equivalent parasitic capacitances,the two-port ECM is obtained.Simulations are carried out to test the effectiveness of the twoport ECM.Using the ECM,the voltage transmission characteristics and their influencing factors are analyzed,depending on which corresponding voltage equalization method is proposed in this paper,and the effect of this method is verified through simulation.