期刊文献+
共找到2篇文章
< 1 >
每页显示 20 50 100
Machine learning algorithm partially reconfigured on FPGA for an image edge detection system
1
作者 Gracieth Cavalcanti Batista Johnny Oberg +3 位作者 Osamu Saotome Haroldo F.de Campos Velho Elcio Hideiti Shiguemori Ingemar Soderquist 《Journal of Electronic Science and Technology》 EI CAS CSCD 2024年第2期48-68,共21页
Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for... Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time. 展开更多
关键词 Dynamic partial reconfiguration(DPR) Field programmable gate array(FPGA)implementation Image edge detection Support vector regression(SVR) Unmanned aerial vehicle(UAV) pose estimation
下载PDF
Searching for complete set of free resource rectangles on FPGA area based on CPTR 被引量:3
2
作者 柴亚辉 沈文枫 +2 位作者 徐炜民 刘觉夫 郑衍衡 《Journal of Shanghai University(English Edition)》 CAS 2011年第5期391-396,共6页
As a coprocessor, field-programmable gate array (FPGA) is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of task... As a coprocessor, field-programmable gate array (FPGA) is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method. 展开更多
关键词 field-programmable gate array (FPGA) partially dynamic reconfigure maximal free rectangle occupied rectangle
下载PDF
上一页 1 下一页 到第
使用帮助 返回顶部