Improving coherent averaging line spectrum detection with phase interpolation and compensation

For the purpose of resolving the problem of performance deterioration introduced by inaccurate phase compensation in existing coherent averaging line spectrum detectors, a modified coherent detector is proposed. The three point interpolation in frequency domain is applied to obtain accurate estimate of phase difference between segments when the segmented length is not an integral multiple of the signal period. Then the segmented data are multiplied by a complex coefficient to remove the phase difference and synchronize the phases of all the segments before coherent averaging. Theoretical analysis shows that there will be a gain of 3.9 dB at most by using the modified detector. The detection performance of the incoher- ent averaging power spectrum detector （AVGPR）, the phase coherent averaging detector, the modified coherent averaging detector are compared with each other by computer simulations. The results coincide basically with the theoretical analysis, which show the superiority of the modified detector to the former two detectors.

Analysis and Design of a Phase Interpolator for Clock and Data Recovery

In this paper,a detailed analysis of a phase interpolator for clock recovery is presented. A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model. The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases. A new encoding pattern is given to solve this problem. Analysis in the circuit domain was also undertaken. The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator. To alleviate this undesired effect, two adjustable-RC buffers are added at the input of the PI. Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed. The power dissipation of the phase interpolator is lmW with a 1.2V power supply. Experiment results show that the phase interpolator has a monotone output phase and good linearity.

A Phase Interpolator CDR with Low-Voltage CML Circuits

In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.

FPGA-based High-precision Measurement Algorithm for the Ultrasonic Echo Time of Flight

Based on the evaluation of advantages and disadvantages of high-precision digital time interval measuring algorithms, and combined with the principle of the typical time-difference ultrasonic flow measurement, the requirements for the measurement of echo time of flight put forward by the ultrasonic flow measurement are analyzed. A new high-precision time interval measurement algorithm is presented, which combines the pulse counting method with the phase delay interpolation. The pulse counting method is used to ensure a large dynamic measuring range, and a double-edge triggering counter is designed to improve the accuracy and reduce the counting quantization error. The phase delay interpolation is used to reduce the quantization error of pulse counting for further improving the time measurement resolution. Test data show that the systexn for the measurement of the ultrasonic echo time of flight based on this algorithm and implemented on an Field Programmable Gate Army（FleA） needs a relatively short time for measurement, and has a measurement error of less than 105 ps.

A 5 Gb/s low area CDR for embedded clock serial links

A multi-standard compatible clock and data recovery circuit （CDR） with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs a first-order digital loop filter, two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area. Meanwhile the tracking range is greater than 4-2200 ppm, making this proposed CDR suitable for the embedded clock serial links. A test chip was fabricated in the 55 nm CMOS process. The measurements show that the test chip can achieve BER 〈 10^-12 and meet the jitter tolerance specification. The test chip occupies 0.19 mma with a 0.0486 mm^2 CDR core, which only consumes 30 mW from a 1.2 V supply at 5 Gb/s.

Wide-range tracking technique for process-variation-robust clock and data recovery applications

A wide-range tracking technique for clock and data recovery(CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design, CDR is not sensitive to process and power supply variations. To verify the technique, the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±6×10-3 at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of <10–12. The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.