A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator ...A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.展开更多
This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation...This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation（WIA） applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator（VCO） is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.展开更多
介绍了一种工作在X波段的低相位噪声、100%国产化频率源的工程设计方法。该方法采用锁相环(PLL)经典电路产生频率信号。分析了PLL相位噪声理论模型,对比了相同封装的国产PLL芯片和进口PLL芯片两种方案,并对实物进行了测试。试验结果表明...介绍了一种工作在X波段的低相位噪声、100%国产化频率源的工程设计方法。该方法采用锁相环(PLL)经典电路产生频率信号。分析了PLL相位噪声理论模型,对比了相同封装的国产PLL芯片和进口PLL芯片两种方案,并对实物进行了测试。试验结果表明,该频率源可稳定输出频率为8.8 GHz的信号。采用国产PLL芯片制作的频率源相位噪声优于采用进口PLL芯片制作的频率源1~2 d B,约为-101 dBc/Hz@1 kHz,-110 d Bc/Hz@100 kHz。展开更多
文摘A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.
基金supported by the National High Technology Research and Development Program of China(No.2011AA040102)
文摘This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation（WIA） applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator（VCO） is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.
文摘介绍了一种工作在X波段的低相位噪声、100%国产化频率源的工程设计方法。该方法采用锁相环(PLL)经典电路产生频率信号。分析了PLL相位噪声理论模型,对比了相同封装的国产PLL芯片和进口PLL芯片两种方案,并对实物进行了测试。试验结果表明,该频率源可稳定输出频率为8.8 GHz的信号。采用国产PLL芯片制作的频率源相位噪声优于采用进口PLL芯片制作的频率源1~2 d B,约为-101 dBc/Hz@1 kHz,-110 d Bc/Hz@100 kHz。
