CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

Small-signal Stability Analysis and Improvement with Phase-shift Phase-locked Loop Based on Back Electromotive Force Observer for VSC-HVDC in Weak Grids

Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.

Simulation of Analog Costas Loop Circuits

The analysis of stability and numerical simulation of Costas loop circuits for the high-frequency signals is a challenging task. The problem lies in the fact that it is necessary to observe very fast time scale of input signals and slow time scale of signal s phases simultaneously. To overcome this difficulty, it is possible to follow the classical ideas of Gardner and Viterbi to construct a mathematical model of Costas loop, in which only slow time change of signal s phases and frequencies is considered. Such an construction, in turn,requires the computation of phase detector characteristic, depending on the waveforms of the considered signals. In this paper, the problems of nonlinear analysis of Costas loops and the approaches to the simulation of the classical Costas loop, the quadrature phase shift keying(QPSK) Costas loop, and the two-phase Costas loop are discussed. The analytical method for the computation of phase detector characteristics of Costas loops is described.

弱交流系统下STATCOM对LCC-HVDC小干扰稳定裕度的影响研究

当电网换相换流器高压直流输电（linecommutated converter based high voltage direct current,LCC-HVDC）逆变侧交流母线处含有静止同步补偿器（static synchronous compensator,STATCOM）时,LCC-HVDC与STATCOM均需要各自的锁相环（phase-locked-loop,PLL）为其控制系统提供基准。该文考虑LCC与STATCOM锁相环各自动态建立含STATCOM的LCC-HVDC系统的小干扰模型,采用经典特征根分析方法,通过对比LCC-HVDC系统与含STATCOM的LCC-HVDC系统二者之间的锁相环与控制系统参数可行域的差异,研究STATCOM对LCC-HVDC小干扰稳定裕度的影响。最后,通过理论计算,对比有无STATCOM投入时LCC-HVDC系统在不同SCR与不同PLL参数下的最大传输有功功率（maximum available power,MAP）及临界短路比（critical short circuit ratio,CSCR）的变化规律。研究结果表明,当LCC-HVDC连接较弱系统时,控制系统之间的耦合作用对LCC锁相环的稳定可行域产生负面影响,可能引发由于LCC锁相环增益过大而导致的整个混合系统的小干扰失稳现象。