ENSO Phase-Locking in an Ocean-Atmosphere Coupled Model FGCM-1.0

The mean climatology and the basic characteristics of the ENSO cycle simulated by a coupled model FGCM-1.0 are investigated in this study. Although with some common model biases as in other directly coupled models, FGCM-1.0 is capable of producing the interannual variability of the tropical Pacific, such as the ENSO phenomenon. The mechanism of the ENSO events in the coupled model can be explained by “delayed oscillator” and “recharge-discharge” hypotheses. Compared to the observations, the simulated ENSO events show larger amplitude with two distinctive types of phase-locking： one with its peak phase-locked to boreal winter and the other to boreal summer. These two types of events have a similar frequency of occurrence, but since the second type of event is seldom observed, it may be related to the biases of the coupled model. Analysis show that the heat content anomalies originate from the central south Pacific in the type of events peaking in boreal summer, which can be attributed to a different background climatology from the normal events. The mechanisms of their evolutions are also discussed.

Coherent beam combination of adaptive fiber laser array with tilt-tip and phase-locking control

We present an experimental study on tilt-tip（TT） and phase-locking（PL） control in a coherent beam combination（CBC） system of adaptive fiber laser array.The TT control is performed using the adaptive fiber-optics collimator（AFOC）,and the PL control is realized by the phase modulator（PM）.Cascaded and simultaneous controls of TT and PL using stochastic parallel gradient descent（SPGD） algorithm are investigated in this paper.Two-fiber-laser-,four-fiber-laser-,and six-fiber-laser-arrays are employed to study the TT and PL control.In the cascaded control system,only one high-speed CMOS camera is used to collect beam data and a computer is used as the controller.In a simultaneous control system one high-speed CMOS camera and one photonic detector（PD） are employed,and a computer and a control circuit based on field programmable gate array（FPGA） are used as the controllers.Experimental results reveal that both cascaded and simultaneous controls of TT using AFOC and PL using PM in fiber laser array are feasible and effective.Cascaded control is more effective in static control situation and simultaneous control can be applied to the dynamic control system directly.The control signals of simultaneous PL and TT disturb each other obviously and TT and PL control may compete with each other,so the control effect is limited.

PHASE-LOCKING OF HIGH POWER GYROTRON OSCILLATOR

The phase-locking process is studied for high-power gyrotron oscillator driven by an external signal. The phase-locking nonlinear differential equations are derived, and the condition of phase-locking is shown and analyzed. The phase-locking signal can be introduced after gyrotron oscillates into saturation or before it. Two different ways of inputting signal make markable influence on the phase-locking process, this phenomenon is discussed. In this paper, the numerical calculations and analysis are given for gyrotron TE13 mode.

CHAOS AND BIFURCATION OF PHASE-LOCKING LOOPS UNDER PERIODIC PERTURBATION

This paper discusses the chaos and bifurcation for equation x+cosxx+asinx =ebsint. By use of the Melnikov method the conditions to have the chaotic behavior and to have subharmonic oscillations are given.

Gigahertz frequency hopping in an optical phase-locked loop for Raman lasers

Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.

Vein visualization enhancement by dual-wavelength phase-locked denoising technology

Visual near-infrared imaging equipment has broad applications in various fields such as venipuncture,facial injections,and safety verification due to its noncontact,compact,and portable design.Currently,most studies utilize near-infrared single-wavelength for image acquisition of veins.However,many substances in the skin,including water,protein,and melanin can create significant background noise,which hinders accurate detection.In this paper,we developed a dual-wavelength imaging system with phase-locked denoising technology to acquire vein image.The signals in the effective region are compared by using the absorption valley and peak of hemoglobin at 700nm and 940nm,respectively.The phase-locked denoising algorithm is applied to decrease the noise and interference of complex surroundings from the images.The imaging results of the vein are successfully extracted in complex noise environment.It is demonstrated that the denoising effect on hand veins imaging can be improved with 57.3%by using our dual-wavelength phase-locked denoising technology.Consequently,this work proposes a novel approach for venous imaging with dual-wavelengths and phase-locked denoising algorithm to extract venous imaging results in complex noisy environment better.

Boosting the Information Transfer Rate of an SSVEP-BCI System Using Maximal-Phase-Locking Value and Minimal-Distance Spatial Filter Banks

For Brain-Computer Interface(BCI) systems, improving the Information Transfer Rate(ITR) is a very critical issue. This study focuses on a Steady-State Visually Evoked Potential(SSVEP)-based BCI because of its advantage of high ITR. Unsupervised Canonical Correlation Analysis(CCA)-based method has been widely employed because of its high efficiency and easy implementation. In a recent study, an ensemble-CCA method based on individual training data was proposed and achieved an excellent performance with ITR of 267 bit/min.A 40-target SSVEP-BCI speller was investigated in this study, using an integration of Minimal-Distance(MD) and Maximal-Phase-locking value(MP) approaches. In the MD approach, a spatial filter is developed to minimize the distance between the training data and the reference sine signal, and in this study, two different types of distance were compared. In the MP approach, a spatial filter is developed to maximize the Phase-Locking Value(PLV)between the training calibration data and the reference sine signal. In addition to the fundamental frequency of stimulation, the harmonics were used to train MD and MP spatial filters, which formed spatial filter banks. The test data epoch was multiplied by the MP and MD spatial filter banks, and the distances and PLVs were extracted as features for recognition. Across 12 subjects with a 0.4 s-data length, the proposed method realized an average classification accuracy and ITR of 93% and 307 bit/min, respectively, which is significantly higher than the current state-of-the-art method. To the best of our knowledge, these results suggest that the proposed method has achieved the highest ITR in SSVEP-BCI studies.

A frequency servo SoC with output power stabilization loop technology for miniaturized atomic clocks

A frequency servo system-on-chip(FS-SoC)featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium(Cs)atomic clocks.The proposed power stabilization loop(PSL)technique,incorporating an off-chip power detector(PD),ensures that the output power of the FS-SoC remains stable,mitigating the impact of power fluctuations on the atomic clock's stability.Additionally,a one-pulse-per-second(1PPS)is employed to syn-chronize the clock with GPS.Fabricated using 65 nm CMOS technology,the measured phase noise of the FS-SoC stands at-69.5 dBc/Hz@100 Hz offset and-83.9 dBc/Hz@1 kHz offset,accompanied by a power dissipation of 19.7 mW.The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7×10^(-11) with 1-s averaging time.

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

An improved arctangent algorithm based on phase-locked loop for heterodyne detection system

We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.

Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

A sapphire fibre thermal probe based on fast Fourier transform and phase-lock loop

A sapphire fibre thermal probe with Cr^3＋ ion-doped end is developed by using the laser heated pedestal growth method. The fluorescence thermal probe offers advantages of compact structure, high performance and ability to withstand high temperature in a detection range from room temperature to 450℃. Based on the fast Fourier transform （FFT）, the fluorescence lifetime is obtained from the tangent function of phase angle of the non-zeroth terms in the FFT result. This method has advantages such as quick calculation, high accuracy and immunity to the background noise. This FFT method is compared with other traditional fitting methods, indicating that the standard deviation of the FFT method is about half of that of the Prony method and about 1/6 of that of the log-fit method. And the FFT method is immune to the background noise involved in a signal. So, the FFT method is an excellent way of processing signals. In addition, a phase-lock amplifier can effectively suppress the noise.

Tunable characteristic of phase-locked quantum cascade laser arrays

A multimode interference(MMI)structure is designed to simplify the fabrication of quantum cascade laser(QCL)phase-locked arrays.The MMI geometry is optimized with a sufficient output channel distance to accommodate conventional photolithography and wet etching process by which power amplifier array is fabricated without using the complicated two-step etching-regrowth or dry etching technique.The far-field pattern with periodically modulated peaks reveals that the beams from the arrays are phase-locked.Furthermore,the frequency tuning performance of the MMI-based phase-locked arrays is studied using the Littrow-configuration external cavity structure.A wavelength tuning range of more than 60 cm^(−1) is demonstrated,which will eventually realize the high power,frequency tunable,large-scale phase-locked arrays,and their application in spectroscopy.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Phase-Locked Loop Based Cancellation of ECG Power Line Interference

Power line(PL)interference is one significant artifact in electrocardiography(ECG)that needs to be reduced to ensure accurate recording of cardiac signals.Because PL interference is non-stationary and has varying frequency,phase,and amplitude in ECG measurement,adaptive techniques are often necessary to track and cancel the interference.In this paper we present a phase-locked loop(PLL)-based adaptive filter to cancel PL interference.The PLL obtains the reference signal that is fed into the adaptive filter to remove the PL interference at the central frequency of 50 Hz.It is found that the technique can effectively cancel PL interference in real ECG signals and,when compared with some existing techniques such as least mean squares(LMS)adaptive filter,the new technique produces better results in terms of signal-to-interference ratio(SIR).

Observation of Phase-Locked States in the Atlantic Multi-Decadal Oscillation(AMO)

We report that the Atlantic Multi-Decadal Oscillation (AMO) shows the same phase-locked states of period 2 and 3 years that have been reported in many other climate indices. In addition, we find that the report by Muller, Curry et al. of an oscillation in the AMO of 9.1 years is a misinterpretation of a maximum in the Fourier spectrum.

Comparative Study of Low-Pass Filter and Phase-Locked Loop Type Speed Filters for Sensorless Control of AC Drives

High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.

Dynamic Free-Spectral-Range Measurement for Fiber Resonator Based on Digital-Heterodyne Optical Phase-Locked Loop

We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10?9 and a dynamic locking accuracy of about 5 × 10?8 are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on.