A 13-bit, 8 MSample/s pipeline A/D converter

A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers （opamps） are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW （including I/O drivers） when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

A Proposed Meta-Reality Immersive Development Pipeline: Generative AI Models and Extended Reality (XR) Content for the Metaverse

The realization of an interoperable and scalable virtual platform, currently known as the “metaverse,” is inevitable, but many technological challenges need to be overcome first. With the metaverse still in a nascent phase, research currently indicates that building a new 3D social environment capable of interoperable avatars and digital transactions will represent most of the initial investment in time and capital. The return on investment, however, is worth the financial risk for firms like Meta, Google, and Apple. While the current virtual space of the metaverse is worth $6.30 billion, that is expected to grow to $84.09 billion by the end of 2028. But the creation of an entire alternate virtual universe of 3D avatars, objects, and otherworldly cityscapes calls for a new development pipeline and workflow. Existing 3D modeling and digital twin processes, already well-established in industry and gaming, will be ported to support the need to architect and furnish this new digital world. The current development pipeline, however, is cumbersome, expensive and limited in output capacity. This paper proposes a new and innovative immersive development pipeline leveraging the recent advances in artificial intelligence (AI) for 3D model creation and optimization. The previous reliance on 3D modeling software to create assets and then import into a game engine can be replaced with nearly instantaneous content creation with AI. While AI art generators like DALL-E 2 and DeepAI have been used for 2D asset creation, when combined with game engine technology, such as Unreal Engine 5 and virtualized geometry systems like Nanite, a new process for creating nearly unlimited content for immersive reality is possible. New processes and workflows, such as those proposed here, will revolutionize content creation and pave the way for Web 3.0, the metaverse and a truly 3D social environment.

3D Model Occlusion Culling Optimization Method Based on WebGPU Computing Pipeline

Nowadays,Web browsers have become an important carrier of 3D model visualization because of their convenience and portability.During the process of large-scale 3D model visualization based on Web scenes with the problems of slow rendering speed and low FPS(Frames Per Second),occlusion culling,as an important method for rendering optimization,can remove most of the occluded objects and improve rendering efficiency.The traditional occlusion culling algorithm(TOCA)is calculated by traversing all objects in the scene,which involves a large amount of repeated calculation and time consumption.To advance the rendering process and enhance rendering efficiency,this paper proposes an occlusion culling with three different optimization methods based on the WebGPU Computing Pipeline.Firstly,for the problem of large amounts of repeated calculation processes in TOCA,these units are moved from the CPU to the GPU for parallel computing,thereby accelerating the calculation of the Potential Visible Sets(PVS);Then,for the huge overhead of creating pipeline caused by too many 3D models in a certain scene,the Breaking Occlusion Culling Algorithm(BOCA)is introduced,which removes some nodes according to building a Hierarchical Bounding Volume(BVH)scene tree to reduce the overhead of creating pipelines;After that,the structure of the scene tree is transmitted to the GPU in the order of depth-first traversal and finally,the PVS is obtained by parallel computing.In the experiments,3D geological models with five different scales from 1:5,000 to 1:500,000 are used for testing.The results show that the proposed methods can reduce the time overhead of repeated calculation caused by the computing pipeline creation and scene tree recursive traversal in the occlusion culling algorithm effectively,with 97%rendering efficiency improvement compared with BOCA,thereby accelerating the rendering process on Web browsers.

A 71mW 8b 125MSample/s A/D Converter

A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.

A 12bit 300MHz Current-Steering CMOS D/A Converter

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.

A 16 bit Stereo Audio ΣΔ A/D Converter

A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.

PIPELINED多值A/D转换器

通过对多值ADC数学表示的分析，指出了多值ADC具有更高的信息密度。本文结合数字电路的开关信号理论，设计了Pipelined三值ADC。该ADC在保证较高转换速度的同时具有相对简单的电路结构。

Pipelined-Flash A/D转换误差分布规律

本文讨论参考文献[1]中两类四元非线性连续函数△ERRdn与△ERRdj之间的定量关系,对误差比率函数ERR100nm%(λcentreT,n)离散点域分布演变所起的决定性作用。定性地归纳各类误差离散点域的分布变化规律,为推出分时段并行A/D转换电路的各种可变参量裕度函数作好准备。

基于D-分割法的直流变换器遗传自抗扰控制器设计

针对光伏发电系统中DC-DC变换器由于负载和工作环境条件变化等扰动引起的输出波动问题,提出一种基于D-分割法的直流变换器遗传自抗扰控制器(ADRC)设计方法。该方法适用于设计光伏发电领域中的双向DC-DC变换器,采用D-分割法获得满足闭环系统鲁棒稳定的ADRC控制器参数范围;利用具有全局寻优能力的遗传算法,按综合性能指标在该范围内进行参数寻优。实验结果表明,所提基于D-分割法的直流变换器遗传自抗扰控制器设计方法能有效抑制微网母线侧的电压波动和负载突变,提高控制器的鲁棒性,增强光伏发电系统的动态响应性能和抗干扰能力。

一种高速A/D转换器时域重构技术研究

A/D转换器在航空航天系统中的重要元器件,随着器件转换时钟频率不断提高而其工作环境不断恶化,如何准确测试其时间参数对于全面评价A/D转换器性能特别重要。目前对于高速A/D转换器时间参数测试,主流方法是通过示波器直接测试其输出,该方法对于示波器采样速度要求比较高。文章提出一种高速A/D转换器时域重构技术,可以通过计算机数字信号处理方法来实现高速A/D转换器时间参数测试,同时避免对示波器采样速度的依赖。同时,在研究高速A/D转换器时域重构技术方法及其应用的基础上,通过了相关试验验证。

Numeric Simulation of Single Passage Ternary Turbulence Model in Hydraulic Torque Converter

Based on the renormalization group theory, a hydraulic torque converter 3 D turbulent single flow passage model is constructed and boundary condition is determined for analyzing the influence of the fluid field characteristic and parameters on the macroscopic model. Numerical simulation of the single fluid path is processed by computational fluid dynamics and the calculated results approach to experimental data well, and especially in low transmission ratio the torque and head results are more close to experimental data than the calculated results of beam theory. This shows that the appropriate ternary analysis method and reasonable assumption of boundary condition may analyze the flow field more precisely and predict the performance of torque converter more accurately.

An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.

A 10bit 2GHz CMOS D/A Converter for High-Speed System Applications

This paper presents a 2GS/s 10bit CMOS digital-to-analog converter （DAC） that consists of two unit current-cell matrixes for 6MSBs and 4LSBs, respectively, trading off between the precision and size of the chip. Current mode logic （CML） is used to ensure high speed,and a double centro-symmetric current matrix is designed by the Q^2 random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2mm × 2.2mm of die area and consumes 790mW with a single 3.3V power supply.

一种14位80 MS/s流水线型A/D转换器设计

基于SMIC 0.18μm CMOS工艺,设计了一种14位80 MS/s的流水线型A/D转换器(ADC)。为了降低ADC整体功耗,首级电路采用2.5 bit无采样保持(SHA-less)结构。进一步,基于套筒式共源-共栅结构提出了一种改进型运放,通过复制尾电流反馈技术和增益提高技术的应用提升了运放的速度和增益,且功耗较低。比较器仅采用动态锁存器以减小级间延迟。还采用了栅压自举开关降低开关导通电阻,提高采样网络带宽和线性度。芯片测试结果表明,在1.8 V电源电压、采样频率为80 MHz的条件下,输入信号频率分别为10 MHz和70 MHz时,ADC的动态参数性能相差不大。其中,输入信号频率为70 MHz时,信噪失真比(SNDR)为72.2 dB,无杂散动态范围(SFDR)为85.82 dB,有效位数(ENOB)为11.7 bit,品质因数(FoM)为0.38 pJ/(conv·step)。

Building Information Modeling-Based Secondary Development System for 3D Modeling of Underground Pipelines

Underground pipeline networks constitute a major component of urban infrastructure,and thus,it is imperative to have an efficient mechanism to manage them.This study introduces a secondary development system to efficiently model underground pipeline networks,using the building information modeling(BIM)-based software Revit.The system comprises separate pipe point and tubulation models.Using a Revit application programming interface(API),the spatial position and attribute data of the pipe points are extracted from a pipeline database,and the corresponding tubulation data are extracted from a tubulation database.Using the Family class in Revit API,the cluster in the self-built library of pipe point is inserted into the spatial location and the attribute data is added;in the same way,all pipeline instances in the pipeline system are created.The extension and localization of the model accelerated the modeling speed.The system was then used in a real construction project.The expansion of the model database and rapid modeling made the application of BIM technology in three-dimensional visualization of underground pipeline networks more convenient.Furthermore,it has applications in pipeline engineering construction and management.

Performance Optimization of Torque Converters Based on Modified 1D Flow Model

A methodology for performance optimization of torque converters is put forward based on the one-dimensional (1D) flow model. It is found that the inaccuracy of 1D flow model for predicting hydraulic performance at the low speed ratio is mainly caused by the separation phenomenon at the stator cascade which is induced by large flow impinging at the pressure side of the stator blades. A semi-empirical separation model is presented and incorporated to the original 1D flow model. It is illustrated that the improved model is able to predict the circumferential velocity components accurately, which can be applied to performance optimization. Then, the Pareto front is obtained by using the genetic algorithm (GA) in order to inspect the coupled relationship among stalling impeller torque capacity, stalling torque ratio and efficiency. The efficiency is maximized on the premise that a target stalling impeller torque capacity and torque ratio are achieved. Finally, the optimized result is verified by the computational fluid dynamics(CFD) simulation, which indicates that the maximal efficiency is increased by 0.96%.

Numerical simulation of the flow field of a flat torque converter

A flexible flat torque converter was proposed to fulfill the requirement of miniaturization and power density maximization for automobiles.Constructed by two arcs joined by lines,the torus was designed directly from design path.The influence of flatness on the performance of the torque converter was evaluated.The software CFX and standard k-ε model were adopted to simulate the internal flow fields of the torque converter under different flatness ratios.The results indicated that the performance of the torque converter got worse as the flatness declined,but the capacity of pump increased.The efficiency and the torque ratio dropped slightly as the flatness ratio decreased.So the torque converter could be squashed appropriately to get high power density without too much efficiency sacrifice.But when the flatness ratio was below 0.2,there was a significant drop in the efficiency.

Discussion on applying an analytical method to optimize the anti-freeze design parameters for underground water pipelines in seasonally frozen areas

Adopting the quasi-three-dimensional （Quasi-3D） numerical method to optimize the anti-freeze design parameters of an underground pipeline usually involves heavy numerical calculations. Here, the fitting formulae between the safe con-veyance distance （SCD） of a water pipeline and six influencing factors are established based on the lowest water temper-ature （LWT） along the pipeline axis direction. With reference to the current widely used anti-freeze design approaches for underground pipelines in seasonally frozen areas, this paper first analyzes the feasibility of applying the maximum frozen penetration （MFP） instead of the mean annual ground surface temperature （MAGST） and soil water content （SWC） to calculate the SCD. The results show that the SCD depends on the buried depth if the MFP is fixed and the variation of the MAGST and SWC combination does not significantly change the SCD. A comprehensive formula for the SCD is estab-lished based on the relationships between the SCD and several primary influencing factors and the interaction among them. This formula involves five easy-to-access parameters： the MFP, buried depth, pipeline diameter, flow velocity, and inlet water temperature. A comparison between the analytical method and the numerical results based on the Quasi-3D method indicates that the two methods are in good agreement overall. The analytic method can be used to optimize the anti-freeze design parameters of underground water pipelines in seasonally frozen areas under the condition of a 1.5 safety coefficient.

血清GSDMD、ACE2在小儿川崎病中的表达水平及临床意义研究

目的 探索血清焦孔素蛋白D(GSDMD)、血管紧张素转化酶2(ACE2)在小儿川崎病(KD)患儿中的表达水平及临床意义。方法 收集2020年1月至2022年1月该院诊治的90例KD患儿为KD组,根据KD患儿是否发生冠状动脉损伤(CAL),将KD组分为CAL组(32例)和非CAL组(58例),选取同期因急性呼吸道感染发热住该院的患儿50例为发热对照组,另选取同期该院儿外科行择期手术的腹股沟斜疝患儿50例为对照组。采用酶联免疫吸附试验检测血清GSDMD、ACE2水平。Pearson相关分析血清GSDMD、ACE2与临床指标的相关性。多因素Logisitic回归分析KD患者发生CAL的影响因素。受试者工作特征(ROC)曲线分析血清GSDMD、ACE2对KD患儿发生CAL的诊断价值。结果 KD组血清GSDMD、ACE2水平高于发热对照组和对照组,差异有统计学意义(均P<0.05)。相比于非CAL组,CAL组KD患儿发热持续时间、丙种球蛋白治疗时间、红细胞沉降率、血小板计数、C反应蛋白、GSDMD、ACE2水平均明显较高,而血钠、白蛋白明显较低,差异有统计学意义(均P<0.05)。Pearson相关分析结果,KD组患儿血清GSDMD、ACE2水平与发热持续时间、丙种球蛋白治疗时间、红细胞沉降率、血小板计数、C反应蛋白呈正相关(均P<0.05),与血钠、白蛋白呈负相关(均P<0.05)。多因素Logistic回归分析结果显示,血清GSDMD、ACE2升高是影响KD患儿发生CAL的独立危险因素。ROC曲线分析结果显示,血清GSDMD、ACE2两项联合检测KD患儿发生CAL的曲线下面积(AUC)及其95%CI为0.918(0.868~0.949),明显大于血清GSDMD、ACE2单项检测的AUC及其95%CI[依次为0.838(0.789~0.887)、0.865(0.811~0.912)],差异有统计学意义(Z=5.116、4.217,均P<0.05)。结论 血清GSDMD、ACE2两项联合检测对于KD患儿发生CAL具有较高的诊断价值。