针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier...针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。展开更多
A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifier...A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.展开更多
针对传统模数转换器(analog to digital convertor,ADC)设计复杂度高、仿真迭代时间长的问题,提出了一种高精度ADC系统设计与建模方法。该方法以10 bit 50 MHz流水线ADC为例,首先选取分离采样架构,进行电路的s域变换理论分析;其次对电...针对传统模数转换器(analog to digital convertor,ADC)设计复杂度高、仿真迭代时间长的问题,提出了一种高精度ADC系统设计与建模方法。该方法以10 bit 50 MHz流水线ADC为例,首先选取分离采样架构,进行电路的s域变换理论分析;其次对电路中各种非理想噪声的表达式进行精确推导,根据系统中的运放功耗指标进行参数优化;最后分别在MATLAB和Cadence软件中建立模型,进行100点蒙特卡洛仿真。仿真结果表明,在TSMC 180 nm工艺失配下,该流水线ADC有效位数达到9.70 bit,无杂散动态范围维持在76 dB附近,微分非线性在0.3 LSB以内,积分非线性在0.5 LSB以内,核心功耗在8 mW,该分析方法在保证流水线ADC优异性能的同时,大幅提高了设计效率。展开更多
Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the ...Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.展开更多
This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power const...This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.展开更多
A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-dom...A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain. This algorithm is designed for high speed and low comparator accuracy application. The comparator offset correction ability is improved. This new approach also promises significant improvements to the spurious-free dynamic range (SFDR), the total harmonic distortion (THD), the signal-to-noise ratio (SNR) and the minor analog and digital circuit modifications. Behavioral simulation results are presented to demonstrate the effectiveness of the algorithm, in which all absolute values of comparator offsets are set to |3Vref/8|. SFDR, THD and SNR are improved, from 34.62-dB, 34.63-dB and 30.33-dB to 60.23-dB, 61.14-dB and 59.35-dB, respectively, for a 10-bit pipeline ADC.展开更多
This paper presents a 10bit 5MS/s pipelined analog-to-digital converter(ADC)for single carrier power line communication transceiver.It's a low-power method by using switched op amp technique,and proposes the switc...This paper presents a 10bit 5MS/s pipelined analog-to-digital converter(ADC)for single carrier power line communication transceiver.It's a low-power method by using switched op amp technique,and proposes the switch capacitor(SC)bias circuitry to solve the startup issue of the current bias.Two common-mode feedback networks are employed to solve the problem of common-mode stability.Removes the sample and hold circuitry(SHA)to further reduce power consumption.Simulation result shows that the proposed ADC achieves 9.6 ENOB,75.8dB SFDR.The power consumption is 0.6 mA for 1.8V supply voltage. Index Terms:Pipelined ADC;switched op amp;switch capacitor bias;展开更多
文摘针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。
文摘A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.
文摘针对传统模数转换器(analog to digital convertor,ADC)设计复杂度高、仿真迭代时间长的问题,提出了一种高精度ADC系统设计与建模方法。该方法以10 bit 50 MHz流水线ADC为例,首先选取分离采样架构,进行电路的s域变换理论分析;其次对电路中各种非理想噪声的表达式进行精确推导,根据系统中的运放功耗指标进行参数优化;最后分别在MATLAB和Cadence软件中建立模型,进行100点蒙特卡洛仿真。仿真结果表明,在TSMC 180 nm工艺失配下,该流水线ADC有效位数达到9.70 bit,无杂散动态范围维持在76 dB附近,微分非线性在0.3 LSB以内,积分非线性在0.5 LSB以内,核心功耗在8 mW,该分析方法在保证流水线ADC优异性能的同时,大幅提高了设计效率。
文摘Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.
基金provided by National Chip Implementation Center(CIC)
文摘This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.
文摘A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain. This algorithm is designed for high speed and low comparator accuracy application. The comparator offset correction ability is improved. This new approach also promises significant improvements to the spurious-free dynamic range (SFDR), the total harmonic distortion (THD), the signal-to-noise ratio (SNR) and the minor analog and digital circuit modifications. Behavioral simulation results are presented to demonstrate the effectiveness of the algorithm, in which all absolute values of comparator offsets are set to |3Vref/8|. SFDR, THD and SNR are improved, from 34.62-dB, 34.63-dB and 30.33-dB to 60.23-dB, 61.14-dB and 59.35-dB, respectively, for a 10-bit pipeline ADC.
文摘This paper presents a 10bit 5MS/s pipelined analog-to-digital converter(ADC)for single carrier power line communication transceiver.It's a low-power method by using switched op amp technique,and proposes the switch capacitor(SC)bias circuitry to solve the startup issue of the current bias.Two common-mode feedback networks are employed to solve the problem of common-mode stability.Removes the sample and hold circuitry(SHA)to further reduce power consumption.Simulation result shows that the proposed ADC achieves 9.6 ENOB,75.8dB SFDR.The power consumption is 0.6 mA for 1.8V supply voltage. Index Terms:Pipelined ADC;switched op amp;switch capacitor bias;
