基于新型环形放大器的低功耗Pipelined SAR ADC

针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放。CSFRA通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗。基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC。该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944μW,其中CSFRA功耗仅为368μW。

List-Serial Pipelined Hardware Architecture for SCL Decoding of Polar Codes

For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.

基于Pipelined结构的电流型CMOS模数转换器电路设计

低功耗设计在当前超大规模集成电路中越来越重要.以电流信号为转换对象,利用电流传输理论,结合电流型CMOS电路设计技术,设计了8位基于Pipelined结构的ADC电路.结果表明,利用电流型CMOS电路可方便地实现电流信号的加减与放大运算,避免了使用传统Pipelined电路结构中的运算放大器电路,因此电路结构简单,可显著降低电路的功耗,提高转换速度,计算机仿真结果表明,电路功能正确.

PIPELINED多值A/D转换器

通过对多值ADC数学表示的分析，指出了多值ADC具有更高的信息密度。本文结合数字电路的开关信号理论，设计了Pipelined三值ADC。该ADC在保证较高转换速度的同时具有相对简单的电路结构。

1.5位pipelined ADC单级传函的数模分析

1.5位结构是构成pipelined ADC的基本单元,总结了2位向1.5位方案传函的演变过程,但对转换的最优性并未证明。在此通过理论分析揭示了ADC及其单级传输函数变换的本质,证明了在Pipeline结构中,ADC单级传输函数演变的本质是:通过单级传函的变化,使整个ADC最终的传输函数与我们所习惯使用的(或者说最初使用的),相差不大于1个LSB,同时在参考电压失调,子DAC输出失调或者增益错误方面获得一定的鲁棒性。

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Optimization of Power Dissipation in Pipelined Analog-to-Digital Converter

Power optimization for pipelined analog-to-digital converter(ADC) was studied. Operational principle of pipelined ADC was discussed and noise voltage caused by two important thermal noise sources, sampling switch and amplifier,was quantitatively analyzed. Method used to minimize power and the values under simple model were presented. Power can be saved by making the sampling and feedback capacitors scale down in the pipeline.And the size of capacitors was limited by thermal noise in high resolution ADC.The equivalent circuits of the two important thermal noise sources were established.Thermal noise was optimally distributed among the pipeline stages,and the relationship between scaling factor and closed loop gain was obtained for minimum power dissipation.Typical closed loop gain was 2 or 4 in pipeline ADC, and the corresponding scaling factor was (1.217) and 1.317.These results can serve as useful guidelines for designers to minimize the ADC′s power consumption.

A FAST FOREGROUND DIGITAL CALIBRATION TECHNIQUE FOR PIPELINED ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.

Deeply pipelined interpolation architecture for full ultra-HD H.265/HEVC video encoding

Fractional motion estimation(FME) improves the video encoding efficiency significantly. However, its high computational complexity limits the real-time processing capability. Therefore, it is a key problem to reduce the implementation complexity of FME, especially in hardware design. This paper presents a novel deeply pipelined interpolation architecture of FME for the real-time realization of H.265/HEVC full Ultra-HD video encoder. First, a pipelined interpolation architecture together with an elegant processing order is proposed to deal with different search positions in parallel without pipeline stall and data conflict. Second, interpolation results sharing strategies are exploited among search positions to reduce the memory cost. Finally, the structure of the interpolation filter is further optimized for an area efficient implementation. As a result, the proposed design costs 41 917 slice LUTs on the Xilinx Kintex-7 FPGA platform with a 308 MHz working frequency. The measured throughput reaches a record of 1.238 Gpixels/s, which is sufficient for the real-time encoding of 8192×4320@ 30 fps video.

Efficient pipelined flow classification for intelligent data processing in IoT

The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things(IoT).In recent years,researchers have tried to develop hardware-based solutions for the classification of Internet packets.Due to higher throughput and shorter delays,these solutions are considered as a major key to improving the quality of services.Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput.The proposed architectures,however,cannot reach a compromise among power consumption,memory usage,and throughput rate.In view of this,the architecture proposed in this paper contains a pipelinebased micro-core that is used in network processors to classify packets.To this end,three architectures have been implemented using the proposed micro-core.The first architecture performs parallel classification based on header fields.The second one classifies packets in a serial manner.The last architecture is the pipeline-based classifier,which can increase performance by nine times.The proposed architectures have been implemented on an FPGA chip.The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput.The architecture has a power consumption of is 1.294w,and its throughput with a frequency of 233 MHz exceeds 147 Gbps.

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

A 27-mW 10-bit 125-MSPS charge domain pipelined ADC with a PVT insensitive boosted charge transfer circuit

A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm^2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.

A 12-bit 250-MS/s Charge-Domain Pipelined Analog-to-Digital Converter with Feed-Forward Common-Mode Charge Control

A feed-forward Common-Mode （CM） charge control circuit for a high-speed Charge-Domain （CO） pipelined Analog-to-Digital Converter （ADC） is presented herein. This study aims at solving the problem whereby the precision of CD pipelined ADCs is restricted by the variation in input CM charge, which can compensate for CM charge errors caused by a variation in CM charge input in real time. Based on the feed-forward CM charge control circuit, a 12-bit 250-MS/s CD pipelined ADC is designed and realized using a 1P6M 0.18-μm CMOS process. The ADC achieved a Spurious Free Dynamic Range （SFDR） of 78.1 dB and a Signal-to-Noise-and-Distortion Ratio （SNDR） of 64.6 dB for a 20.1-MHz input; a SFDR of 74.9 dB and SNDR of 62.0 dB were achieved for a 239.9-MHz input at full sampling rate. The variation in signal-to-noise ratio was less than 3 dB over a 0-1.2 V input CM voltage range. The power consumption of the prototype ADC is only 85 mW at 1.8 V supply, and it occupies an active die area of 2.24 mm^2.

A pipelined Reed-Solomon decoder based on a modified step-by-step algorithm

We propose a pipelined Reed-Solomon(RS) decoder for an ultra-wideband system using a modified stepby-step algorithm. To reduce the complexity, the modified step-by-step algorithm merges two cases of the original algorithm. The pipelined structure allows the decoder to work at high rates with minimum delay. Consequently, for RS(23,17) codes, the proposed architecture requires 42.5% and 24.4% less area compared with a modified Euclidean architecture and a pipelined degree-computationless modified Euclidean architecture, respectively. The area of the proposed decoder is 11.3% less than that of the previous step-by-step decoder with a lower critical path delay.

A 10-bit 250 MSPS charge-domain pipelined ADC with replica controlled PVT insensitive BCT circuit

A low power 10-bit 250 MSPS charge-domain （CD） pipelined analog-to-digital converter （ADC） is introduced. The ADC is implemented in MOS bucket-brigade devices （BBDs） based CD pipelined architecture. A replica controlled boosted charge transfer （BCT） circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. The ADC achieves an SFDR of 64.4 dB, an SNDR of 56.9 dB and an ENOB of 9.2 for a 9.9 MHz input; and an SFDR of 63.1 dB, an SNR of 55.2 dB, an SNDR of 54.5 dB and an ENOB of 8.7 for a 220.5 MHz input at full sampling rate. The DNL is ＋0.5/- 0.55 LSB and INL is ＋0.8/- 0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm2.

Simulink Behavioral Modeling of a 10-bit Pipelined ADC

The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters （ADCs）. All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters （white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages）. Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.

New insights into the deposition of natural gas hydrate on pipeline surfaces:A molecular dynamics simulation study

Natural gas hydrate(NGH)can cause pipeline blockages during the transportation of oil and gas under high pressures and low temperatures.Reducing hydrate adhesion on pipelines is viewed as an efficient way to prevent NGH blockages.Previous studies suggested the water film can greatly increase hydrate adhesion in gas-dominant system.Herein,by performing the molecular dynamics simulations,we find in water-dominant system,the water film plays different roles in hydrate deposition on Fe and its corrosion surfaces.Specifically,due to the strong affinity of water on Fe surface,the deposited hydrate cannot convert the adsorbed water into hydrate,thus,a water film exists.As water affinities decrease(Fe>Fe_(2)O_(3)>FeO>Fe_(3)O_(4)),adsorbed water would convert to amorphous hydrate on Fe_(2)O_(3)and form the ordered hydrate on FeO and Fe_(3)O_(4)after hydrate deposition.While absorbed water film converts to amorphous or to hydrate,the adhesion strength of hydrate continuously increases(Fe<Fe_(2)O_(3)<FeO<Fe_(3)O_(4)).This is because the detachment of deposited hydrate prefers to occur at soft region of liquid layer,the process of which becomes harder as liquid layer vanishes.As a result,contrary to gas-dominant system,the water film plays the weakening roles on hydrate adhesion in water-dominant system.Overall,our results can help to better understand the hydrate deposition mechanisms on Fe and its corrosion surfaces and suggest hydrate deposition can be adjusted by changing water affinities on pipeline surfaces.

Sacrificial piles as a countermeasure against local scour around underwater pipelines

Local scour around pipelines crossing rivers or in marine environments is a significant concern.It can lead to failure of the pipelines resulting in environmental side effects and economic losses.This study developed an experimental method to reduce local scour around pipelines with a steady flow of clear water by installing cylindrical and cubical sacrificial piles.Three sizes of sacrificial piles were examined in a linear arrangement.Sacrificial piles were installed on the upstream side of the pipeline at three distances.Maximum scour depth reduction rates below the pipeline were computed.The results showed that sacrificial piles could protect a pipeline from local scour.A portion of scoured sediment around the sacrificial piles was deposited beneath the pipeline.This sediment accumulation reduced the scour depth beneath the pipeline.Analysis of the experimental results demonstrated that the size of piles(d),the spacing between piles,and the distance between the pipe and piles(Xp)were the variables that reduced the maximum scour beneath the pipeline with a diameter of D.For the piles with d=0.40D and 0.64D,X_(p)=4OD was the optimal distance to install a group of piles,and cubical piles could mitigate scour more effectively than cylindrical piles under similar conditions.For the piles with d=D,the greatest reduction in scour depth was achieved at X_(p)=50D with any desired spacings between piles,and cylindrical piles in this dimension could protect the pipeline against scour more effectively than cubical piles.

Comparison of nonlinear modeling methods for the composite rubber clamp

The cubic stiffness force model(CSFM)and Bouc-Wen model(BWM)are introduced and compared innovatively.The unknown coefficients of the nonlinear models are identified by the genetic algorithm combined with experiments.By fitting the identified nonlinear coefficients under different excitation amplitudes,the nonlinear vibration responses of the system are predicted.The results show that the accuracy of the BWM is higher than that of the CSFM,especially in the non-resonant region.However,the optimization time of the BWM is longer than that of the CSFM.

Experimental and Finite Element Analysis of Corroded High-Pressure Pipeline Repaired by Laminated Composite

Repairs of corroded high-pressure pipelines are essential for fluids transportation under high pressure.One of the methods used in their repairs is the use of layered composites.The composite used must have the necessary strength.Therefore,the experiments and analytical solutions presented in this paper are performed according to the relevant standards and codes,including ASME PCC-2,ASME B31.8S,ASME B31.4,ISO 24817 and ASME B31.G.In addition,the experimental tests are replicated numerically using the finite element method.Setting the strain gauges at different distances from the defect location,can reduce the nonlinear effects,deformation,and fluctuations due to the high pressure.The direct relationship between the depth of an axial defect and the stress concentration is observed at the inner side edges of the defect.Composite reparation reduces the non-linearities related to the sharp variation of the geometry and a more reliable numerical simulation could be performed.