Temperature-dependent bias-stress-induced electrical instability of amorphous indium-gallium-zinc-oxide thin-film transistors

The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.

Energy distribution extraction of negative charges responsible for positive bias temperature instability

A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability（PBTI） stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.

Positive Bias Temperature Instability and Hot Carrier Injection of Back Gate Ultra-thin-body In0.53Ga0.47As-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor

Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.

Positive gate bias stress-induced hump-effect in elevated-metal metal-oxide thin film transistors

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-metal metal-oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the back-channel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device （L=2 μm）. It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.

Response of the low-pressure hot-filament discharge plasma to a positively biased auxiliary disk electrode

In a steady-state plasma,the loss rate of plasma particles to the chamber wall and surfaces in contact with plasma is balanced by the ionization rate of background neutrals in the hot-filament discharges.The balance between the loss rate and ionization rate of plasma particles(electrons and ions)maintains quasi-neutrality of the bulk plasma.In the presence of an external perturbation,it tries to retain its quasi-neutrality condition.In this work,we studied how the properties of bulk plasma are affected by an external DC potential perturbation.An auxiliary biased metal disk electrode was used to introduce a potential perturbation to the plasma medium.A single Langmuir probe and an emissive probe,placed in the line of the discharge axis,were used for the characterization of the bulk plasma.It is observed that only positive bias to the auxiliary metal disk increases the plasma potential,electron temperature,and plasma density but these plasma parameters remain unaltered when the disk is biased with a negative potential with respect to plasma potential.The observed plasma parameters for two different-sized,positively as well as negatively biased,metal disks are compared and found inconsistent with the existing theoretical model at large positive bias voltages.The role of the primary energetic electrons population in determining the plasma parameters is discussed.The experimentally observed results are qualitatively explained on the basis of electrostatic confinement arising due to the loss of electrons to a biased metal disk electrode.

Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and Al2O3 Dielectric

Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.

Influence of ultra-thin TiN thickness(1.4 nm and 2.4 nm) on positive bias temperature instability(PBTI)of high-k/metal gate nMOSFETs with gate-last process

The positive bias temperature instability（PBTI） degradations of high-k/metal gate（HK/MG） n MOSFETs with thin TiN capping layers（1.4 nm and 2.4 nm） are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI（90℃,125℃, 160℃） are studied and activation energy（Ea） values（0.13 eV and 0.15 eV） are extracted. Although the equivalent oxide thickness（EOT） values of two TiN thickness values are almost similar（0.85 nm and 0.87 nm）, the 2.4-nm TiN one（thicker Ti N capping layer） shows better PBTI reliability（13.41% at 0.9 V, 90℃, 1000 s）. This is due to the better interfacial layer/high-k（IL/HK） interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.

Towards Positivity:A Large-Scale Diachronic Sentiment Analysis of the Humanities and Social Sciences in China

With its rising number of publications and expanding international collaborations,China's humanities and social sciences(HSS)research is displaying its potential for global prominence.Researchers have been exploring the development of China's HSS from different perspectives.However,the examinations from the perspective of sentiment analysis are scanty.Our aim is then to examine the sentiment features in Chinese HSS academic writing,by analyzing a large-scale corpus with over 275 million characters and with a time span from 2000 to 2020.Considering that most studies only focused on abstracts,we examined both the abstracts and the full texts,as well as a direct comparison between them.We found that Chinese HSS academic writing has evolved to be more positively biased in the past two decades,showing an upward trend in the use of positive words and a slight downward trend in the use of negative words.However,the upward trend of positive words in the full texts is not that clear,resembling a fluctuating pattern.Regarding the comparison,the abstracts are more likely to use positive words while the full texts tend to use more negative words.These phenomena can be explained with the social cognitive theory,in that they may be shaped by a joint force of the nature of human beings,the nature of language,the particular socio-cultural background in China and the features of the academic genre.

Degradation characteristics and mechanism of PMOSFETs under NBT-PBT-NBT stress

Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature （NBT-PBT-NBT） stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.

Impacts of NBTI/PBTI on power gated SRAM

A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.

Carrier phase-based ionospheric observables using PPP models

The ionosphere is one of the major error sources in Global Navigation Satellite System （GNSS） posi- tioning, navigation and timing. Estimating the ionospheric delays precisely is of great interest in the GNSS community. To date, GNSS observables for ionospheric estimation are most commonly based on carrier phase smoothed code measurements. However, leveling errors, which affect the performance of ionospheric modeling and differential code bias （DCB） estimation, exist in the carrier phase smoothed code observations. Such leveling errors are caused by the multipath and the short-term variation of DCB. To reduce these leveling errors, this paper investigates and estimates the ionospheric delays based on carrier phase measurements without the leveling errors. The line-of-sight ionospheric observables with high precision are calculated using precise point positioning （PPP） techniques, in which carrier phase measurements are the principal observables. Ionosphere-free and UofC PPP models are applied and compared for their effectiveness to minimize the leveling errors. To assess the leveling errors, single difference of ionospheric observables for a short baseline is examined. Results show that carrier phase- derived ionospheric observables from PPP techniques can effectively reduce the leveling errors. Furthermore, we compared the PPP ionosphere estimation model with the conventional carrier phase smoothed code method to assess the bias consistency and investigate the biases in the ionospheric observables.

Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process

Positive bias temperature instability（PBTI） characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 e V, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift.

Spontaneous positive exchange bias effect in SrFeO_(3-x)/SrCoO_(3-x) epitaxial bilayer

A novel phenomenon of spontaneous positive exchange bias(PEB)is reported in SrFeO_(3-x)/SrCoO_(3-x) epitaxial bilayer without undergoing any magnetic field treatment.When inserting a thick SrTiO3(STO)nonmagnetic spacer(about 6 nm)into the bilayer interface,this phenomenon still exists.Based on a series of testing means,the spontaneous PEB effect is supposed to be mainly related to short-range ferromagnetic(FM)exchange coupling at the interface when there is no STO spacer.As the STO interlayer reaches up to a certain thickness,shortrange coupling interaction basically disappears.At this time,the long-range dipole field may be responsible for the coupling of the FM and antiferromagnetic(AFM)layer across the nonmagnetic STO and then leads to the same bias effect.Our discoveries provide a new way to realize and manipulate spontaneous exchange bias-based spintronics devices,such as magnetic recording heads and spin valves.