Analytical model for power dissipation in cell membranes in suspensions exposed to electric fields

Due to interaction among cells, it is too complex to build an exactanalytical model for the power dissipation within the cell membrane in suspensions exposed toexternal fields. An approximate equivalence method is proposed to resolve this problem. Based on theeffective medium theory, the transmembrane voltage on cells in suspensions was investigated by theequivalence principle. Then the electric field in the cell membrane was determined. Finally,analytical solutions for the power dissipation within the cell membrane in suspensions exposed toexternal fields were derived according to the Joule principle. The equations show that theconductive power dissipation is predominant within the cell membrane in suspensions exposed todirect current or lower frequencies, and dielectric power dissipation prevails at high frequenciesexceeding the relaxation frequency of the exposed membrane.

Power dissipation characteristics of great power and super high speed semiconductor switch

The power dissipation characteristics of pulsed power switch reversely switched dynistors （RSDs） are investigated in this paper. According to the expressions of voltage on RSD, derived from the plasma bipolar drift model and the RLC circuit equations of RSD main loop, the simulation waveforms of current and voltage on RSD are acquired through iterative calculation by using the fourth order Runge-Kutta method, then the curve of transient power on RSD versus time is obtained. The result shows that the total dissipation on RSD is trivial compared with the pulse discharge energy and the commutation dissipation can be nearly ignored compared with the quasi-static dissipation. These characteristics can make the repetitive frequency of RSD increase largely. The experimental results prove the validity of simulation calculations. The influence factors on power dissipation are discussed. The power dissipation increases with the increase of the peak current and the n-base width and with the decrease of n-base doping concentration. In order to keep a low power dissipation, it is suggested that the n-base width should be smaller than 320μm when doping concentration is 1.0×10^14cm^-3 while the doping concentration should be higher than 5.8×10^13cm^-3 when n-base width is 270μm.

Power dissipation in oxide-confined 980-nm vertical-cavity surface-emitting lasers

We presented 980-nm oxide-confined vertical-cavity surface-emitting lasers （VCSELs） with a 16 -um oxide aperture. Optical power, voltage, and emission wavelength are measured in an ambient temperature range of 5 ℃-80 ℃. Measurements combined with an empirical model are used to analyse the power dissipation in the device and the physical mechanism contributing to the thermal rollover phenomenon in VCSEL. It is found that the carrier leakage induced selfheating in the active region and the Joule heating caused by the series resistance are the main sources of power dissipation. In addition, carrier leakage induced self-heating increases as the injection current increases, resulting in a rapid decrease of the internal quantum efficiency, which is a dominant contribution to the thermal rollover of the VCSEL at a larger current. Our study provides useful guidelines to design a 980-nm oxide-confined VCSEL for thermal performance enhancement.

Thermal stability improvement of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations using non-uniform finger spacing

A method of non-uniform finger spacing is proposed to enhance thermal stability of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations. Temperature distribution on the emitter fingers of a multi-finger SiGe heterojunction bipolar transistor is studied using a numerical electro-thermal model. The results show that the SiGe heterojunction bipolar transistor with non-uniform finger spacing has a small temperature difference between fingers compared with a traditional uniform finger spacing heterojunction bipolar transistor at the same power dissipation. What is most important is that the ability to improve temperature non-uniformity is not weakened as power dissipation increases. So the method of non-uniform finger spacing is very effective in enhancing the thermal stability and the power handing capability of power device. Experimental results verify our conclusions.

Estimation of the sheath power dissipation induced by ion cyclotron resonance heating

During ion cyclotron resonance heating,the sheath power dissipation caused by ion acceleration in the radio frequency(RF)sheath is one of the main causes of RF power loss in the tokamak edge region.To estimate the power dissipation of an RF sheath in the ion cyclotron range of frequency(ICRF),a 1 D fluid model for the multi-component plasma sheath driven by a sinusoidal disturbance current in the ICRF is presented.By investigation of the sheath potential and ion flux at the wall,it is shown that the larger frequency and lower amplitude of the disturbance current can cause smaller sheath power dissipation.The effect of the energetic ion on the sheath power dissipation depends on the disturbance current.For large amplitude of disturbance current,the increase in the concentration and energy of the energetic ion leads to a decrease in sheath power dissipation.While for a small disturbance current,the sheath power dissipation demonstrates non-monotonic variation with the concentration and energy of the energetic ion.In addition,the sheath power dissipation is found to have a small increase in the presence of light impurity ions with low valence.

GA-BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS

In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library, a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view. The simulation on 1SCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02. Compared with the traditional Monte Carlo-based technique, the new approach presented in this paper is more effective.

Dynamic Power Dissipation Control Method for Real-Time Processors Based on Hardware Multithreading

In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.

Effects of Dummy Thermal Vias on Interconnect Delay and Power Dissipation of Very Large Scale Integration Circuits

The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.

POWER OPTIMIZATION OF FINITE STATE MACHINE BASED ON GENETIC ALGORITHM

Using state assignment to minimize power dissipation and area for finite state ma-chines is computationally hard. Most of published results show that the reduction of switchingactivity often trades with area penalty. In this paper, a new approach is proposed. Experimentalresults show a significant reduction of switching activity without area penalty compared withprevious publications.

A Novel Power Optimization Method by Minimum Comparator Number Algorithm for Pipeline ADCs

The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.

Partition-based Low Power DFT Methodology for System-on-chips

This paper presents a partition-based Design-for- Test （DFT） technique to reduce the power consumption during scan-based testing. This method is based on partitioning the chip into several independent scan domains. By enabling the scan domains alternatively, only a fraction of the entire chip will be active at the same time, leading to low power consumption during test. Therefore, it will significantly reduce the possibility of Electronic Migration and Overheating. In order to prevent the drop of fault coverage, wrappers on the boundaries between scan domains are employed. This paper also presents a detailed design flow based on Electronics Design Automation （EDA） tools from Synopsy~ to implement the proposed test structure. The proposed DFT method is experimented on a state-of-theart System-ou-chips （SOC）. The simulation results show a significant reduction in both average and peak power dissipation without sacrificing the fault coverage and test time. This SOC has been taped out in TSMC and finished the final test m ADVANTEST.

Estimating Power for FPGAs Based on Signal Probability Theory

Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays （FPGAs）, thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array （FPGA） electronic design automation （EDA） tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.

Topology Optimization for Steady-State Navier-Stokes Flow Based on Parameterized Level Set Based Method

In this paper,we consider solving the topology optimization for steady-state incompressibleNavier-Stokes problems via a new topology optimization method called parameterized level set method,which can maintain a relatively smooth level set function with a local optimality condition.The objective of topology optimization is to􀀀nd an optimal con􀀀guration of theuid and solid materials that minimizes power dissipation under a prescribeduid volume fraction constraint.An arti􀀀cial friction force is added to the Navier-Stokes equations to apply the no-slip boundary condition.Although a great deal of work has been carried out for topology optimization ofuidow in recent years,there are few researches on the topology optimization ofuidow with physical body forces.To simulate theuidow in reality,the constant body force(e.g.,gravity)is considered in this paper.Several 2D numerical examples are presented to discuss the relationships between the proposed method with Reynolds number and initial design,and demonstrate the feasibility and superiority of the proposed method in dealing with unstructuredmesh problems.Three 3D numerical examples demonstrate the proposedmethod is feasible in three-dimensional.

Ring Oscillator for 60 Meter Bandwidth

The 60-meter band range is tremendously useful in telecommunication,military and governmental applications.The I.T.U.(International Telecommunication Union)required isolationism to former radio frequency services because the various frequency bands are extremely overloaded.The allocation of new frequency bands are a lengthy procedure as well as time taking.As a result,the researchers use bidirectional,amateur radio frequency communication for 60-meter band,usually the frequency slot of 5250-5450 KHz,although the entire band is not essentially obtainable for all countries.For transmission and reception of these frequencies,a local oscillator is used in the mixer unit to generate the local signal for mixing the input and reference signals.For this function different type of oscillators are used.In this paper,a three-stage ring oscillator is designed with 1 V supply.Ring oscillators(RO)is the base to explore like to identifying,specify with modelling resources in the disparity in behaviour of the circuit in terms of industrialized design and layout parameters.This type of oscillators are free from noise as inductor is not used to the circuit as in LC oscillator,Heartly oscillator,Colpitt and tuned oscillators.The present approach of circuit designing,the scaling of CMOS(Complementary Metal Oxide Semiconductor)transistor will moderate,the procedure variability.In the forthcoming article,a ring oscillator with fixed capacitor(1 pF)and with variable capacitors(1 to 100 pF)is analysed.The frequency analysis with different capacitor is performed.The total delay of 3-stage oscillator is 4.82 ns with 5.2 MHz oscillation frequency.The overall Power dissipation of the circuit is 1.852μWat 1 V supply.The simulation analysis is performed on 45 nm CMOS technology with both transistor width are 278 and 420 nm.

Hot deformation behavior of spray forming LSHR alloy using constitutive equation and processing map

Flow behaviors of spray forming low solvus high refractory (LSHR) alloy were investigated using hot compression tests performed on a Gleeble?3500 thermal mechanical simulator at temperatures of 1020?1150 °C and strain rates of 0.0003?1.0 s?1. The constitutive equation was established, power dissipation (η) maps and hot processing maps were plotted. The microstructure evolution and dislocation distribution of domains with different values of η in power dissipation maps were also observed. The results show that the flow stress increases with decreasing temperature and increasing strain rate. The activation energy of the spray forming LSHR alloy is 1243.86 kJ/mol. When the value of η is 0.36 at the strain of 0.5, the domain in the processing map shows characteristics of typical dynamic recrystallization (DRX) and low dislocation density. According to the microstructure evolution and processing maps, the optimum processing condition for good hot workability of spray forming LSHR alloy can be summed up as:temperature range 1110?1150 °C; strain rate range 0.01?0.3 s?1.

Hot Deformation Behavior of 2124 Al Alloy

The mechanical behavior of 2124 Al alloy produced by powder metallurgy was investigated with compression test at different temperatures and strain rates. The tests were performed in the temperature range of 300℃～500℃ and at strain rates from 0.001 s^-1 to 1.0 s^-1. The compression flow curves exhibited an initial sharp increase with strain, followed by monotonous hardening. The maximum stress decreased with decreasing strain rate and increasing temperature. The hot deformation characteristics of the material were studied using processing maps. The domain of safety and unsafe regime were identified and validated through microstructural examination.

A novel interconnect-optimal repeater insertion model with target delay constraint in 65 nm CMOS

Repeater optimization is the key for SOC （System on Chip） interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD （computer aided design） tool for interconnect planning in nanometre SOC.

CLASSIFYING WESTERN NORTH PACIFIC TROPICAL CYCLONES BY PHYSICAL INDEX SYSTEM

The classification of tropical cyclones(TCs) is significant to obtaining their temporal and spatial variation characteristics in the context of dramatic-changing global climate. A new TCs clustering method by using K-means clustering algorithm with nine physical indexes is proposed in the paper. Each TC is quantified into an 11-dimensional vector concerning trajectory attributes, time attributes and power attributes. Two recurving clusters(cluster A and E)and three straight-moving clusters(cluster B, C and D) are categorized from the TC best-track dataset of the western North Pacific(WNP) over the period of 1949-2013, and TCs' properties have been analyzed and compared in different aspects. The calculation results of coefficient variation(CV) and Nash-Sutcliffe efficiency(NSE) reveal a high level of intra-cluster cohesiveness and inter-cluster divergence, which means that the physical index system could serve as a feasible method of TCs classification. The clusters are then analyzed in terms of trajectory, lifespan, seasonality, trend,intensity and Power Dissipation Index(PDI). The five classified clusters show distinct features in TCs' temporal and spatial development discipline. Moreover, each cluster has its individual motion pattern, variation trend, influence region and impact degree.

Dual-Port Content Addressable Memory for Cache Memory Applications

Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory(DPCAM).In addition,it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm(NFRA)to reduce the cost overhead of the cache controller and improve the cache access latency.The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory.Moreover,it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM.However,an estimation of the power dissipation showed that DPCAM consumes about 7%greater than a set-associative cache memory of the same size.These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.

Efficient Energy Optimized Faithful Adder with Parallel Carry Generation

Abstract:Approximate computing has received significant attention in the design of portable CMOS hardware for error-tolerant applications.This work proposes an approximate adder that to optimize area delay and achieve energy efficiency using Parallel Carry(PC)generation logic.For‘n’bits in input,the proposed algorithm use approximate addition for least n/2 significant bits and exact addition for most n/2 significant bits.A simple OR logic with no carry propagation is used to implement the approximate part.In the exact part,addition is performed using 4-bit adder blocks that implement PC at block level to reduce node capacitance in the critical path.Evaluations reveal that the maximum error of the proposed adder confines not more than 2n/2.As an enhancement of the proposed algorithm,we use the Error Recovery(ER)module to reduce the average error.Synthesis results of Proposed-PC(P-PC)and Proposed-PCER(P-PCER)adders with n-16 in 180nm Application Specific Integrated Circuit(ASIC)PDK technology revealed 44.2%&41.7%PDP reductions and 43.4%&40.7%ADP reductions,respectively compared to the latest best approximate design compared.The functional and driving effectiveness of proposed adders are examined through digital image processing applications.