Impacts of NBTI/PBTI on power gated SRAM

A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.

Estimating Power for FPGAs Based on Signal Probability Theory

Power dissipation has become one of the key optimization conditions in logic design on field programmable gate arrays （FPGAs）, thus the power estimation is necessary for logic design optimization. Nowadays, signal activity data created by logic simulation based on test vectors is essential to be used to determine the toggle rate of each signals and blocks in power estimation tools provided by field programmable gate array （FPGA） electronic design automation （EDA） tools. The accuracy of power estimation highly depends on the quality of test vectors, especially, pattern coverage. As probability distribution can describe the uncertainty signals, this work provides an algorithm which can estimate FPGAs power more effectively and accurately by using signal probability distribution rather than test vectors.

Simulation of the sensitive region to SEGR in power MOSFETs

Single event gate rupture（SEGR） is a very important failure mode for power MOSFETs when used in aerospace applications,and the cell regions are widely considered to be the most sensitive to SEGR.However, experimental results show that SEGR can also happen in the gate bus regions.In this paper,we used simulation tools to estimate three structures in power MOSFETs,and found that if certain conditions are met,areas other than cell regions can become sensitive to SEGR.Finally,some proposals are given as to how to reduce SEGR in different regions.

DimRouter： A Multi-Mode Router Architecture for Higher Energy-Proportionality of On-Chip Networks

In the dark silicon era, many independent components of many-core processors are becoming voluntarily inactive due to the constraint of power consumption on a chip. However, to keep network connectivity, the on-chip interconnection must still be kept activated and wastes considerable energy to avoid the isolation of these inactive components, harming the energy-proportionality of the whole processor chip. In this paper, we propose a novel design to provide more energy- proportional on-chip connection without damaging the network connectivity. To achieve this goal, we redesign the router architecture. The new architecture, DimRouter, supports three modes： normal, dark and dim. In the dim mode, only part of the router is active and provides flexible connection while the dark mode puts all router elements in the asleep state. Moreover, to maximize the number of dark routers, we also propose a reconfiguration algorithm based on degree-constrained Steiner Tree. The evaluation result under synthetic traffic shows that the new design can reduce the energy consumption up to 85% compared with the common design. For real application traffic, the new design can also save average 46% energy consumption with 4% performance improvement.

DSOI—a novel structure enabling adjust circuit dynamically

A double silicon on insulator（DSOI） structure was introduced based on fully depleted SOI（FDSOI）technology.The circuit performance could be adjusted dynamically through the separate back gate electrodes applied to N-channel and P-channel devices.Based on DSOI ring oscillator（OSC）,this paper focused on the theoretical analysis and electrical test of how the OSC＇s frequency being influenced by the back gate electrodes（soi2n,soi2p）.The testing results showed that the frequency and power consumption of OSC could change nearly linearly along with the back gate bias.According to the different requirements of the circuit designers,the circuit performance could be improved by positive soi2 n and negative soi2 p,and the power consumption could be reduced by negative soi2n and positive soi2p.The best compromise between performance and power consumption of the circuit could be achieved by appropriate back gate biasing.

Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications

We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 cells.At the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area penalty.The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.